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serge-rsserge-rs
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checker: improve prim-DB FIFO
1 parent 3c182dd commit 4f02393

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4 files changed

+193
-60
lines changed

4 files changed

+193
-60
lines changed

‎planning/src/file_io/pln_blif_file.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -462,16 +462,17 @@ bool BLIF_file::checkBlif() noexcept {
462462
//string written = pr_write_yaml(LUT5);
463463
//string written = pr_write_yaml(DFFRE);
464464
//string written = pr_write_yaml( DSP19X2 );
465-
string written = pr_write_yaml( DSP38 );
465+
//string written = pr_write_yaml( DSP38 );
466+
string written = pr_write_yaml( FIFO36K );
466467
flush_out(true);
467468
if (written.empty()) {
468469
lprintf("\t\t FAIL: pr_write_yaml() FAILED\n\n");
469470
} else {
470471
lprintf("\t written: %s\n\n", written.c_str());
471472
if (0) {
472473
lprintf("\n ");
473-
for (int bb = 17; bb >= 0; bb--) {
474-
lprintf(" \"B[%i]\",", bb);
474+
for (int bb = 35; bb >= 0; bb--) {
475+
lprintf(" \"WR_DATA[%i]\",", bb);
475476
}
476477
lputs();
477478
lputs();
@@ -612,8 +613,9 @@ uint BLIF_file::printPrimitives(std::ostream& os, bool instCounts) const noexcep
612613
if (n_clocks) {
613614
::sprintf(ncs_buf, " #clock_pins= %u", n_clocks);
614615
}
615-
os_printf(os, " [%u] %s i:%u o:%u %s\n",
616-
t, pn, pr_num_inputs(pt), n_outputs, ncs_buf);
616+
os_printf(os, " [%u] %s i:%u o:%u %s %s\n",
617+
t, pn, pr_num_inputs(pt), n_outputs, ncs_buf,
618+
pr_is_core_fabric(pt) ? "core" : "");
617619
}
618620
}
619621

‎planning/src/file_io/pln_primitives.cpp

Lines changed: 146 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ using std::string;
2525
"I_BUF_DS",
2626
"I_DDR",
2727
"I_DELAY",
28+
"I_FAB",
2829
"IO_BUF",
2930
"IO_BUF_DS",
3031
"I_SERDES",
@@ -40,6 +41,7 @@ using std::string;
4041
"O_BUFT_DS",
4142
"O_DDR",
4243
"O_DELAY",
44+
"O_FAB",
4345
"O_SERDES",
4446
"O_SERDES_CLK",
4547
"PLL",
@@ -61,9 +63,40 @@ using std::string;
6163

6264
{ "Q" }, // DFFRE
6365

64-
{ "Z1", "DLY_B1", "Z2", "DLY_B2" }, // DSP19X2
65-
66-
{ "Z", "DLY_B" }, // DSP38
66+
// DSP19X2
67+
{
68+
// Z1[18:0]:
69+
"Z1[17]", "Z1[16]", "Z1[15]", "Z1[14]", "Z1[13]", "Z1[12]", "Z1[11]", "Z1[10]",
70+
"Z1[9]", "Z1[8]", "Z1[7]", "Z1[6]", "Z1[5]", "Z1[4]", "Z1[3]", "Z1[2]",
71+
"Z1[1]", "Z1[0]",
72+
73+
// DLY_B1[8:0]:
74+
"DLY_B1[7]", "DLY_B1[6]", "DLY_B1[5]", "DLY_B1[4]", "DLY_B1[3]", "DLY_B1[2]",
75+
"DLY_B1[1]", "DLY_B1[0]"
76+
77+
// Z2[18:0]:
78+
"Z2[17]", "Z2[16]", "Z2[15]", "Z2[14]", "Z2[13]", "Z2[12]", "Z2[11]", "Z2[10]",
79+
"Z2[9]", "Z2[8]", "Z2[7]", "Z2[6]", "Z2[5]", "Z2[4]", "Z2[3]", "Z2[2]",
80+
"Z2[1]", "Z2[0]",
81+
82+
// DLY_B2[8:0]:
83+
"DLY_B2[7]", "DLY_B2[6]", "DLY_B2[5]", "DLY_B2[4]", "DLY_B2[3]", "DLY_B2[2]",
84+
"DLY_B2[1]", "DLY_B2[0]"
85+
},
86+
87+
// DSP38
88+
{
89+
// Z[37:0]
90+
"Z[36]", "Z[35]", "Z[34]", "Z[33]", "Z[32]", "Z[31]", "Z[30]", "Z[29]", "Z[28]", "Z[27]", "Z[26]",
91+
"Z[25]", "Z[24]", "Z[23]", "Z[22]", "Z[21]", "Z[20]", "Z[19]", "Z[18]", "Z[17]", "Z[16]", "Z[15]",
92+
"Z[14]", "Z[13]", "Z[12]", "Z[11]", "Z[10]", "Z[9]", "Z[8]", "Z[7]",
93+
"Z[6]", "Z[5]", "Z[4]", "Z[3]", "Z[2]", "Z[1]", "Z[0]",
94+
95+
// DLY_B[17:0]
96+
"DLY_B[16]", "DLY_B[15]", "DLY_B[14]", "DLY_B[13]", "DLY_B[12]", "DLY_B[11]", "DLY_B[10]",
97+
"DLY_B[9]", "DLY_B[8]", "DLY_B[7]", "DLY_B[6]", "DLY_B[5]", "DLY_B[4]", "DLY_B[3]",
98+
"DLY_B[2]", "DLY_B[1]", "DLY_B[0]"
99+
},
67100

68101
{ "O" }, // FCLK_BUF
69102

@@ -73,19 +106,32 @@ using std::string;
73106
"RD_DATA2", "EMPTY2", "FULL2", "ALMOST_EMPTY2", "ALMOST_FULL2",
74107
"PROG_EMPTY2", "PROG_FULL2", "OVERFLOW2", "UNDERFLOW2" },
75108

76-
// FIFO36K
77-
{ "RD_DATA", "EMPTY", "FULL", "ALMOST_EMPTY", "ALMOST_FULL",
78-
"PROG_EMPTY", "PROG_FULL", "OVERFLOW", "UNDERFLOW" },
109+
// FIFO36K
110+
{
111+
// RD_DATA[DATA_WRITE_WIDTH-1:0]:
112+
"RD_DATA[35]", "RD_DATA[34]", "RD_DATA[33]", "RD_DATA[32]", "RD_DATA[31]", "RD_DATA[30]",
113+
"RD_DATA[29]", "RD_DATA[28]", "RD_DATA[27]", "RD_DATA[26]", "RD_DATA[25]", "RD_DATA[24]",
114+
"RD_DATA[23]", "RD_DATA[22]", "RD_DATA[21]", "RD_DATA[20]", "RD_DATA[19]", "RD_DATA[18]",
115+
"RD_DATA[17]", "RD_DATA[16]", "RD_DATA[15]", "RD_DATA[14]", "RD_DATA[13]", "RD_DATA[12]",
116+
"RD_DATA[11]", "RD_DATA[10]", "RD_DATA[9]", "RD_DATA[8]", "RD_DATA[7]", "RD_DATA[6]",
117+
"RD_DATA[5]", "RD_DATA[4]", "RD_DATA[3]", "RD_DATA[2]", "RD_DATA[1]", "RD_DATA[0]",
118+
119+
"EMPTY", "FULL", "ALMOST_EMPTY", "ALMOST_FULL",
120+
"PROG_EMPTY", "PROG_FULL",
121+
"OVERFLOW", "UNDERFLOW"
122+
},
79123

80124
{ "O" }, // I_BUF
81125
{ "O" }, // I_BUF_DS
82126

83127
{ "Q" }, // I_DDR
84128

85-
{ "O", "DLY_TAP_VALUE" }, // I_DELAY
129+
{ "O", "DLY_TAP_VALUE" }, // I_DELAY
130+
131+
{ "O" }, // I_FAB
86132

87-
{ "O" }, // IO_BUF
88-
{ "O" }, // IO_BUF_DS
133+
{ "O" }, // IO_BUF
134+
{ "O" }, // IO_BUF_DS
89135

90136
// I_SERDES
91137
{ "CLK_OUT", "Q", "DATA_VALID", "DPA_LOCK", "DPA_ERROR" },
@@ -107,6 +153,8 @@ using std::string;
107153

108154
{ "O", "DLY_TAP_VALUE" }, // O_DELAY
109155

156+
{ "O" }, // O_FAB
157+
110158
// O_SERDES
111159
{ "OE_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
112160

@@ -143,28 +191,82 @@ using std::string;
143191

144192
// DSP19X2
145193
{
146-
"A1[8]", "A1[7]", "A1[6]", "A1[5]", "A1[4]", "A1[3]", "A1[2]", "A1[1]", "A1[0]",
147-
"B1[9]", "B1[8]", "B1[7]", "B1[6]", "B1[5]", "B1[4]", "B1[3]", "B1[2]", "B1[1]", "B1[0]",
148-
"CLK", "RESET", "LOAD_ACC", "UNSIGNED_A", "UNSIGNED_B",
149-
"SATURATE", "ROUND", "SUBTRACT"
194+
// A1[9:0]:
195+
"A1[8]", "A1[7]", "A1[6]", "A1[5]", "A1[4]", "A1[3]", "A1[2]", "A1[1]", "A1[0]",
196+
197+
// B1[8:0]:
198+
"B1[7]", "B1[6]", "B1[5]", "B1[4]", "B1[3]", "B1[2]", "B1[1]", "B1[0]",
199+
200+
// A2[9:0]:
201+
"A2[8]", "A2[7]", "A2[6]", "A2[5]", "A2[4]", "A2[3]", "A2[2]", "A2[1]", "A2[0]",
202+
203+
// B2[8:0]:
204+
"B2[7]", "B2[6]", "B2[5]", "B2[4]", "B2[3]", "B2[2]", "B2[1]", "B2[0]",
205+
206+
"CLK", "RESET",
207+
208+
// ACC_FIR[4:0]:
209+
"ACC_FIR[3]", "ACC_FIR[2]", "ACC_FIR[1]", "ACC_FIR[0]",
210+
211+
// FEEDBACK[2:0]:
212+
"FEEDBACK[1]", "FEEDBACK[0]",
213+
214+
"LOAD_ACC",
215+
"UNSIGNED_A", "UNSIGNED_B",
216+
"SATURATE",
217+
218+
// SHIFT_RIGHT[4:0]:
219+
"SHIFT_RIGHT[3]", "SHIFT_RIGHT[2]", "SHIFT_RIGHT[1]", "SHIFT_RIGHT[0]",
220+
221+
"ROUND", "SUBTRACT"
150222
},
151223

152224
// DSP38
153225
{
154-
"A[19]", "A[18]", "A[17]", "A[16]", "A[15]", "A[14]", "A[13]", "A[12]", "A[11]", "A[10]",
155-
"A[9]", "A[8]", "A[7]", "A[6]", "A[5]", "A[4]", "A[3]", "A[2]", "A[1]", "A[0]",
156-
"B[17]", "B[16]", "B[15]", "B[14]", "B[13]", "B[12]", "B[11]", "B[10]", "B[9]", "B[8]",
157-
"B[7]", "B[6]", "B[5]", "B[4]", "B[3]", "B[2]", "B[1]", "B[0]",
158-
"CLK",
226+
// A[19:0]:
227+
"A[18]", "A[17]", "A[16]", "A[15]", "A[14]", "A[13]", "A[12]", "A[11]", "A[10]",
228+
"A[9]", "A[8]", "A[7]", "A[6]", "A[5]", "A[4]", "A[3]", "A[2]", "A[1]", "A[0]",
229+
230+
// B[17:0]:
231+
"B[16]", "B[15]", "B[14]", "B[13]", "B[12]", "B[11]", "B[10]", "B[9]", "B[8]",
232+
"B[7]", "B[6]", "B[5]", "B[4]", "B[3]", "B[2]", "B[1]", "B[0]",
233+
234+
// ACC_FIR[5:0]:
235+
"ACC_FIR[4]", "ACC_FIR[3]", "ACC_FIR[2]", "ACC_FIR[1]", "ACC_FIR[0]",
236+
237+
"CLK", "RESET",
238+
239+
// FEEDBACK[2:0]:
240+
"FEEDBACK[1]", "FEEDBACK[0]",
241+
242+
"LOAD_ACC",
243+
"SATURATE",
244+
245+
// SHIFT_RIGHT[5:0]
246+
"SHIFT_RIGHT[4]", "SHIFT_RIGHT[3]", "SHIFT_RIGHT[2]", "SHIFT_RIGHT[1]", "SHIFT_RIGHT[0]",
247+
248+
"ROUND",
249+
"SUBTRACT",
250+
"UNSIGNED_A",
251+
"UNSIGNED_B"
159252
},
160253

161254
{ "I" }, // FCLK_BUF
162255

163256
// FIFO18KX2
164257
{ },
165258

166-
// FIFO36K
167-
{ },
259+
// FIFO36K
260+
{ "RESET", "WR_CLK", "RD_CLK", "WR_EN", "RD_EN",
261+
262+
// WR_DATA[DATA_WRITE_WIDTH-1:0]:
263+
"WR_DATA[35]", "WR_DATA[34]", "WR_DATA[33]", "WR_DATA[32]", "WR_DATA[31]", "WR_DATA[30]",
264+
"WR_DATA[29]", "WR_DATA[28]", "WR_DATA[27]", "WR_DATA[26]", "WR_DATA[25]", "WR_DATA[24]",
265+
"WR_DATA[23]", "WR_DATA[22]", "WR_DATA[21]", "WR_DATA[20]", "WR_DATA[19]", "WR_DATA[18]",
266+
"WR_DATA[17]", "WR_DATA[16]", "WR_DATA[15]", "WR_DATA[14]", "WR_DATA[13]", "WR_DATA[12]",
267+
"WR_DATA[11]", "WR_DATA[10]", "WR_DATA[9]", "WR_DATA[8]", "WR_DATA[7]", "WR_DATA[6]",
268+
"WR_DATA[5]", "WR_DATA[4]", "WR_DATA[3]", "WR_DATA[2]", "WR_DATA[1]", "WR_DATA[0]"
269+
},
168270

169271
{ "I", "EN" }, // I_BUF
170272
{ "I_P", "I_N", "EN" }, // I_BUF_DS
@@ -175,8 +277,10 @@ using std::string;
175277
{ "I", "DLY_LOAD", "DLY_ADJ",
176278
"DLY_INCDEC", "CLK_IN" },
177279

178-
{ "I" }, // IO_BUF
179-
{ "I" }, // IO_BUF_DS
280+
{ "I" }, // I_FAB
281+
282+
{ "I" }, // IO_BUF
283+
{ "I" }, // IO_BUF_DS
180284

181285
// I_SERDES
182286
{ "D", "RST", "BITSLIP_ADJ", "EN", "CLK_IN",
@@ -202,6 +306,8 @@ using std::string;
202306
{ "I", "DLY_LOAD", "DLY_ADJ",
203307
"DLY_INCDEC", "CLK_IN" },
204308

309+
{ "I" }, // O_FAB
310+
205311
// O_SERDES // TMP. INCOMPLETE: D is a bus
206312
{ "D", "RST", "DATA_VALID", "CLK_IN", "OE_IN",
207313
"CHANNEL_BOND_SYNC_IN", "PLL_LOCK", "PLL_CLK" },
@@ -257,6 +363,7 @@ using std::string;
257363

258364
{ "CLK_IN" }, // I_DELAY
259365

366+
{ }, // I_FAB
260367
{ }, // IO_BUF
261368
{ }, // IO_BUF_DS
262369

@@ -277,8 +384,8 @@ using std::string;
277384
{ }, // O_BUFT_DS
278385

279386
{ }, // O_DDR
280-
281387
{ }, // O_DELAY
388+
{ }, // O_FAB
282389

283390
{ "CLK_IN", "PLL_CLK" }, // O_SERDES
284391

@@ -357,7 +464,18 @@ uint pr_num_clocks(Prim_t pt) noexcept {
357464
return V.size();
358465
}
359466

360-
void pr_get_inputs(Prim_t pt, vector<string>& INP) {
467+
bool pr_is_core_fabric(Prim_t t) noexcept {
468+
if (pr_is_LUT(t) or pr_is_DSP(t) or pr_is_DFF(t))
469+
return true;
470+
if (t == CARRY or pr_is_FIFO(t) or pr_is_RAM(t) or
471+
t == I_FAB or t == O_FAB) {
472+
return true;
473+
}
474+
475+
return false;
476+
}
477+
478+
void pr_get_inputs(Prim_t pt, vector<string>& INP) noexcept {
361479
INP.clear();
362480
uint i = pt;
363481
assert(i <= Prim_MAX_ID);
@@ -366,7 +484,7 @@ void pr_get_inputs(Prim_t pt, vector<string>& INP) {
366484
INP = _id2inputs[i];
367485
}
368486

369-
void pr_get_outputs(Prim_t pt, vector<string>& OUT) {
487+
void pr_get_outputs(Prim_t pt, vector<string>& OUT) noexcept {
370488
OUT.clear();
371489
uint i = pt;
372490
assert(i <= Prim_MAX_ID);
@@ -575,13 +693,13 @@ string pr_write_yaml(Prim_t pt) noexcept {
575693

576694
fos << "name: " << primName << endl;
577695
fos << "desc: ";
578-
if (pt >= LUT1 and pt <= LUT6)
696+
if (pr_is_LUT(pt))
579697
os_printf(fos, "%u-input lookup table (LUT)", pr_num_inputs(pt));
580698
fos << endl;
581699

582-
fos << "category: core_fabric" << endl;
583-
fos << endl;
700+
os_printf(fos, "category: %s\n", pr_is_core_fabric(pt) ? "core_fabric" : "");
584701

702+
fos << endl;
585703
fos << "ports:" << endl;
586704

587705
vector<string> V;

‎planning/src/file_io/pln_primitives.h

Lines changed: 39 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -29,30 +29,32 @@ enum Prim_t {
2929
I_BUF_DS = 12,
3030
I_DDR = 13,
3131
I_DELAY = 14,
32-
IO_BUF = 15,
33-
IO_BUF_DS = 16,
34-
I_SERDES = 17,
35-
LUT1 = 18,
36-
LUT2 = 19,
37-
LUT3 = 20,
38-
LUT4 = 21,
39-
LUT5 = 22,
40-
LUT6 = 23,
41-
O_BUF = 24,
42-
O_BUF_DS = 25,
43-
O_BUFT = 26,
44-
O_BUFT_DS = 27,
45-
O_DDR = 28,
46-
O_DELAY = 29,
47-
O_SERDES = 30,
48-
O_SERDES_CLK = 31,
49-
PLL = 32,
50-
TDP_RAM18KX2 = 33,
51-
TDP_RAM36K = 34,
52-
53-
X_UNKNOWN = 35,
54-
55-
Y_UPPER_GUARD = 36
32+
I_FAB = 15,
33+
IO_BUF = 16,
34+
IO_BUF_DS = 17,
35+
I_SERDES = 18,
36+
LUT1 = 19,
37+
LUT2 = 20,
38+
LUT3 = 21,
39+
LUT4 = 22,
40+
LUT5 = 23,
41+
LUT6 = 24,
42+
O_BUF = 25,
43+
O_BUF_DS = 26,
44+
O_BUFT = 27,
45+
O_BUFT_DS = 28,
46+
O_DDR = 29,
47+
O_DELAY = 30,
48+
O_FAB = 31,
49+
O_SERDES = 32,
50+
O_SERDES_CLK = 33,
51+
PLL = 34,
52+
TDP_RAM18KX2 = 35,
53+
TDP_RAM36K = 36,
54+
55+
X_UNKNOWN = 37,
56+
57+
Y_UPPER_GUARD = 38
5658
};
5759

5860
// valid IDs are from 1 to Prim_MAX_ID inclusive
@@ -81,8 +83,19 @@ uint pr_num_inputs(Prim_t pt) noexcept;
8183
uint pr_num_outputs(Prim_t pt) noexcept;
8284
uint pr_num_clocks(Prim_t pt) noexcept;
8385

84-
void pr_get_inputs(Prim_t pt, std::vector<std::string>& INP);
85-
void pr_get_outputs(Prim_t pt, std::vector<std::string>& OUT);
86+
inline bool pr_is_LUT(Prim_t t) noexcept { return t >= LUT1 and t <= LUT6; }
87+
inline bool pr_is_DSP(Prim_t t) noexcept { return t == DSP19X2 or t == DSP38; }
88+
inline bool pr_is_DFF(Prim_t t) noexcept { return t == DFFNRE or t == DFFRE; }
89+
inline bool pr_is_FIFO(Prim_t t) noexcept { return t == FIFO18KX2 or t == FIFO36K; }
90+
91+
inline bool pr_is_RAM(Prim_t t) noexcept {
92+
return t == TDP_RAM18KX2 or t == TDP_RAM36K;
93+
}
94+
95+
bool pr_is_core_fabric(Prim_t t) noexcept;
96+
97+
void pr_get_inputs(Prim_t pt, std::vector<std::string>& INP) noexcept;
98+
void pr_get_outputs(Prim_t pt, std::vector<std::string>& OUT) noexcept;
8699

87100
bool is_I_SERDES_output_term(const std::string& term) noexcept;
88101
bool is_O_SERDES_output_term(const std::string& term) noexcept;

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