Merge pull request #723 from os-fpga/fix_compilation_after_merge

fix compilation after OpenFPGA merge

Author: serge-dsa

CMakeLists.txt

@@ -135,6 +135,7 @@ FILE(COPY ${PACKER_SRC_DIR}/cluster.cpp
           ${PACKER_SRC_DIR}/output_clustering.h
           ${PACKER_SRC_DIR}/cluster_router.cpp
           ${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
+          ${PACKER_SRC_DIR}/pack.cpp
           DESTINATION
           ${VPR_DEST_DIR}/src/pack)
 
@@ -170,19 +171,19 @@ message(STATUS "NOTE: PATCHING base/vpr_api.cpp ..")
 set(DIFF_FILE ${PATCH_DIR}/base_fix/DIFF/vpr_api_cpp.diff)
 apply_patch(${DIFF_FILE}  ${TARGET_DIR}  "base/vpr_api.cpp")
 
-message(STATUS "NOTE: OVERWRITING base/read_.*")
-file(COPY
-    ${PATCH_DIR}/base_fix/PATCHED/read_blif.cpp
-    ${PATCH_DIR}/base_fix/PATCHED/read_circuit.cpp
-    ${PATCH_DIR}/base_fix/PATCHED/read_circuit.h
-    ${PATCH_DIR}/base_fix/PATCHED/read_options.cpp
-    ${PATCH_DIR}/base_fix/PATCHED/read_options.h
-    DESTINATION ${TARGET_DIR})
-message(STATUS "NOTE: COPIED ${PATCH_DIR}/base_fix/PATCHED/read_.*\n       to ${TARGET_DIR}/\n")
-
-message(STATUS "NOTE: PATCHING base/SetupVPR.cpp ..")
-set(DIFF_FILE ${PATCH_DIR}/base_fix/DIFF/SetupVPR_cpp.diff)
-apply_patch(${DIFF_FILE}  ${TARGET_DIR}  "base/SetupVPR.cpp")
+#message(STATUS "NOTE: OVERWRITING base/read_.*")
+#file(COPY
+#    ${PATCH_DIR}/base_fix/PATCHED/read_blif.cpp
+#    ${PATCH_DIR}/base_fix/PATCHED/read_circuit.cpp
+#    ${PATCH_DIR}/base_fix/PATCHED/read_circuit.h
+#    ${PATCH_DIR}/base_fix/PATCHED/read_options.cpp
+#    ${PATCH_DIR}/base_fix/PATCHED/read_options.h
+#    DESTINATION ${TARGET_DIR})
+#message(STATUS "NOTE: COPIED ${PATCH_DIR}/base_fix/PATCHED/read_.*\n       to ${TARGET_DIR}/\n")
+
+#message(STATUS "NOTE: PATCHING base/SetupVPR.cpp ..")
+#set(DIFF_FILE ${PATCH_DIR}/base_fix/DIFF/SetupVPR_cpp.diff)
+#apply_patch(${DIFF_FILE}  ${TARGET_DIR}  "base/SetupVPR.cpp")
 
 message(STATUS "NOTE: PATCHING base/vpr_context.h ..")
 set(DIFF_FILE ${PATCH_DIR}/base_fix/DIFF/vpr_context_h.diff)

include/base_fix/PATCHED/netlist_writer.cpp

@@ -1,5 +1,5 @@
 #include "read_circuit.h"
-#include "read_blif_RS.h"
+#include "read_blif.h"
 #include "read_interchange_netlist.h"
 #include "atom_netlist.h"
 #include "atom_netlist_utils.h"
@@ -43,14 +43,6 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu
             circuit_format = e_circuit_format::BLIF;
         } else if (name_ext[1] == ".eblif") {
             circuit_format = e_circuit_format::EBLIF;
-        } else if (name_ext[1] == ".v") {
-            circuit_format = e_circuit_format::VERILOG;
-        }  else if (name_ext[1] == ".edif") {
-            circuit_format = e_circuit_format::EDIF;
-        }  else if (name_ext[1] == ".edn") {
-            circuit_format = e_circuit_format::EDIF;
-        }  else if (name_ext[1] == ".edf") {
-            circuit_format = e_circuit_format::EDIF;
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_ATOM_NETLIST, "Failed to determine file format for '%s' expected .blif or .eblif extension",
                             circuit_file);
@@ -66,20 +58,6 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu
             case e_circuit_format::EBLIF:
                 netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
                 break;
-            case e_circuit_format::VERILOG:
-            #ifdef ENABLE_VERIFIC
-                circuit_format = e_circuit_format::EBLIF;
-                netlist = read_blif_from_vrilog(circuit_format, circuit_file, user_models, library_models, vpr_setup, top_mod);
-            #else
-                VPR_FATAL_ERROR(VPR_ERROR_ATOM_NETLIST,
-                                "Unable to identify circuit file format for '%s'. Expect [blif|eblif|fpga-interchange]! as verilog support is disabled\n",
-                                circuit_file);
-            #endif
-                break;
-            case e_circuit_format::EDIF:
-                circuit_format = e_circuit_format::EDIF;
-                netlist = read_blif_from_edif(circuit_format, circuit_file, user_models, library_models);
-                break;
             case e_circuit_format::FPGA_INTERCHANGE:
                 netlist = read_interchange_netlist(circuit_file, arch);
                 break;

include/base_fix/PATCHED/read_blif.cpp

@@ -7,9 +7,7 @@
 enum class e_circuit_format {
     AUTO,            ///<Infer from file extension
     BLIF,            ///<Strict structural BLIF
-    EBLIF, //Structural blif with extensions
-    VERILOG, // verilog netlist
-    EDIF,
+    EBLIF,           ///<Structural blif with extensions
     FPGA_INTERCHANGE ///<FPGA Interhange logical netlis format
 };