Skip to content

Commit 1af8cd9

Browse files
serge-dsaserge-dsa
authored
Merge pull request #772 from os-fpga/checker_add_prim_clock_pins
checker: added primitive clock pins (initial development)
2 parents f4a53b5 + 5d5ab54 commit 1af8cd9

File tree

10 files changed

+196
-144
lines changed

10 files changed

+196
-144
lines changed

‎planning/src/RS/rsCheck.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,10 @@ static bool do_check_blif(CStr cfn) {
7676
flush_out(true);
7777
if (chk_ok) {
7878
ls << " === BLIF is OK." << endl;
79+
if (tr >= 4 or bfile.trace_ >= 4) {
80+
flush_out(true);
81+
lprintf(" ltrace()= %u pln_blif_trace= %u\n", tr, bfile.trace_);
82+
}
7983
return true;
8084
}
8185

‎planning/src/file_readers/pln_blif_file.cpp

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -365,12 +365,13 @@ bool BLIF_file::checkBlif() noexcept {
365365
createNodes();
366366

367367
if (trace_ >= 5) {
368+
printPrimitives(ls);
368369
printNodes(ls);
369-
lputs();
370+
flush_out(true);
370371
}
371372
if (trace_ >= 6) {
372373
printCarryNodes(ls);
373-
lputs();
374+
flush_out(true);
374375
}
375376

376377
bool link_ok = linkNodes();
@@ -491,6 +492,20 @@ uint BLIF_file::printNodes(std::ostream& os) const noexcept {
491492
return n;
492493
}
493494

495+
uint BLIF_file::printPrimitives(std::ostream& os) const noexcept {
496+
os << endl;
497+
os_printf(os, "======== primitive types (%u) :\n", Prim_MAX_ID);
498+
for (uint t = 1; t < Prim_MAX_ID; t++) {
499+
CStr pn = primt_name(Prim_t(t));
500+
assert(pn and pn[0]);
501+
os_printf(os, " [%u] %s\n", t, pn);
502+
}
503+
504+
os << endl;
505+
os.flush();
506+
return Prim_MAX_ID;
507+
}
508+
494509
uint BLIF_file::countCarryNodes() const noexcept {
495510
uint nn = numNodes();
496511
if (nn == 0)
@@ -499,7 +514,7 @@ uint BLIF_file::countCarryNodes() const noexcept {
499514
uint cnt = 0;
500515
for (uint i = 1; i <= nn; i++) {
501516
const Node& nd = nodePool_[i];
502-
if (nd.ptype_ == CARRY_CHAIN)
517+
if (nd.ptype_ == CARRY)
503518
cnt++;
504519
}
505520

@@ -523,7 +538,7 @@ uint BLIF_file::printCarryNodes(std::ostream& os) const noexcept {
523538

524539
for (uint i = 1; i <= nn; i++) {
525540
const Node& nd = nodePool_[i];
526-
if (nd.ptype_ != CARRY_CHAIN)
541+
if (nd.ptype_ != CARRY)
527542
continue;
528543
CStr pts = nd.cPrimType();
529544
assert(pts);

‎planning/src/file_readers/pln_blif_file.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,7 @@ struct BLIF_file : public fio::MMapReader
177177
uint printInputs(std::ostream& os, CStr spacer = nullptr) const noexcept;
178178
uint printOutputs(std::ostream& os, CStr spacer = nullptr) const noexcept;
179179
uint printNodes(std::ostream& os) const noexcept;
180+
uint printPrimitives(std::ostream& os) const noexcept;
180181

181182
uint countCarryNodes() const noexcept;
182183
uint printCarryNodes(std::ostream& os) const noexcept;

‎planning/src/file_readers/pln_primitives.cpp

Lines changed: 122 additions & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,9 @@ namespace {
1313
static const char* _enumNames[] = {
1414
"A_ZERO",
1515
"BOOT_CLOCK",
16-
"CARRY_CHAIN",
16+
"CARRY",
1717
"CLK_BUF",
18+
"DFFNRE",
1819
"DFFRE",
1920
"DSP19X2",
2021
"DSP38",
@@ -52,136 +53,151 @@ namespace {
5253
{}, // 0
5354

5455
{ "O" }, // BOOT_CLOCK
55-
{ "O", "COUT" }, // CARRY_CHAIN
56+
{ "O", "COUT" }, // CARRY
5657

5758
{ "O" }, // CLK_BUF
5859

60+
{ "Q" }, // DFFNRE
61+
5962
{ "Q" }, // DFFRE
6063

61-
{ "Z1", "DLY_B1", "Z2", "DLY_B2" }, // DSP19X2 = 5,
64+
{ "Z1", "DLY_B1", "Z2", "DLY_B2" }, // DSP19X2
6265

63-
{ "Z", "DLY_B" }, // DSP38 = 6,
66+
{ "Z", "DLY_B" }, // DSP38
6467

65-
// FIFO18KX2 = 7,
68+
// FIFO18KX2
6669
{ "RD_DATA1", "EMPTY1", "FULL1", "ALMOST_EMPTY1", "ALMOST_FULL1",
6770
"PROG_EMPTY1", "PROG_FULL1", "OVERFLOW1", "UNDERFLOW1",
6871
"RD_DATA2", "EMPTY2", "FULL2", "ALMOST_EMPTY2", "ALMOST_FULL2",
6972
"PROG_EMPTY2", "PROG_FULL2", "OVERFLOW2", "UNDERFLOW2" },
7073

71-
// FIFO36K = 8,
74+
// FIFO36K
7275
{ "RD_DATA", "EMPTY", "FULL", "ALMOST_EMPTY", "ALMOST_FULL",
7376
"PROG_EMPTY", "PROG_FULL", "OVERFLOW", "UNDERFLOW" },
7477

75-
{ "O" }, // I_BUF = 9,
76-
{ "O" }, // I_BUF_DS = 10,
77-
78-
{ "Q" }, // I_DDR = 11,
79-
80-
{ "O", "DLY_TAP_VALUE" }, // I_DELAY = 12,
81-
82-
{ "O" }, // IO_BUF = 13,
83-
{ "O" }, // IO_BUF_DS = 14,
84-
85-
86-
/* I_SERDES
87-
CLK_OUT:
88-
dir: output
89-
desc: Fabric clock output
90-
Q[WIDTH-1:0]:
91-
dir: output
92-
desc: Data output
93-
DATA_VALID:
94-
dir: output
95-
desc: DATA_VALID output
96-
DPA_LOCK:
97-
dir: output
98-
desc: DPA_LOCK output
99-
DPA_ERROR:
100-
dir: output
101-
desc: DPA_ERROR output
102-
*/
103-
{ "CLK_OUT", "Q", "DATA_VALID", "DPA_LOCK", "DPA_ERROR" },
78+
{ "O" }, // I_BUF
79+
{ "O" }, // I_BUF_DS
10480

81+
{ "Q" }, // I_DDR
10582

106-
{ "Y" }, // LUT1 = 16,
107-
{ "Y" }, // LUT2 = 17,
108-
{ "Y" }, // LUT3 = 18,
109-
{ "Y" }, // LUT4 = 19,
110-
{ "Y" }, // LUT5 = 20,
111-
{ "Y" }, // LUT6 = 21,
83+
{ "O", "DLY_TAP_VALUE" }, // I_DELAY
11284

113-
{ "O" }, // O_BUF = 22,
114-
{ "O", "O_P", "O_N" }, // O_BUF_DS = 23,
85+
{ "O" }, // IO_BUF
86+
{ "O" }, // IO_BUF_DS
11587

116-
{ "O" }, // O_BUFT = 24,
117-
{ "O", "O_P", "O_N" }, // O_BUFT_DS = 25,
88+
// I_SERDES
89+
{ "CLK_OUT", "Q", "DATA_VALID", "DPA_LOCK", "DPA_ERROR" },
11890

119-
{ "Q" }, // O_DDR = 26,
91+
{ "Y" }, // LUT1
92+
{ "Y" }, // LUT2
93+
{ "Y" }, // LUT3
94+
{ "Y" }, // LUT4
95+
{ "Y" }, // LUT5
96+
{ "Y" }, // LUT6
12097

121-
{ "O", "DLY_TAP_VALUE" }, // O_DELAY = 27,
98+
{ "O" }, // O_BUF
99+
{ "O", "O_P", "O_N" }, // O_BUF_DS
122100

123-
/* O_SERDES
124-
OE_OUT:
125-
dir: output
126-
desc: Output tri-state enable output (to O_BUFT or inferred tri-state signal)
127-
Q:
128-
dir: output
129-
desc: Data output (Connect to output port, buffer or O_DELAY)
130-
CHANNEL_BOND_SYNC_OUT:
131-
dir: output
132-
*/
133-
{ "OE_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
101+
{ "O" }, // O_BUFT
102+
{ "O", "O_P", "O_N" }, // O_BUFT_DS
134103

104+
{ "Q" }, // O_DDR
135105

136-
/* O_SERDES_CLK
137-
CLK_EN:
138-
dir: input
139-
desc: Gates output OUTPUT_CLK
140-
OUTPUT_CLK:
141-
dir: output
142-
desc: Clock output (Connect to output port, buffer or O_DELAY)
143-
type: reg
144-
default: 1'b0
145-
PLL_LOCK:
146-
dir: input
147-
desc: PLL lock input
148-
PLL_CLK:
149-
dir: input
150-
desc: PLL clock input
151-
*/
152-
{ "OUTPUT_CLK" },
106+
{ "O", "DLY_TAP_VALUE" }, // O_DELAY
153107

108+
// O_SERDES
109+
{ "OE_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
154110

155-
/* PLL
156-
CLK_OUT:
157-
dir: output
158-
CLK_OUT_DIV2:
159-
dir: output
160-
CLK_OUT_DIV3:
161-
dir: output
162-
CLK_OUT_DIV4:
163-
dir: output
164-
SERDES_FAST_CLK:
165-
dir: output
166-
LOCK:
167-
dir: output
168-
*/
111+
// O_SERDES_CLK
112+
{ "OUTPUT_CLK" },
113+
114+
// PLL
169115
{ "CLK_OUT", "CLK_OUT_DIV2",
170116
"CLK_OUT_DIV3", "CLK_OUT_DIV4",
171117
"SERDES_FAST_CLK", "LOCK" },
172118

173-
174-
// TDP_RAM18KX2 = 31,
119+
// TDP_RAM18KX2
175120
{ "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2",
176121
"RPARITY_A1", "RPARITY_B1", "RPARITY_A2", "RPARITY_B2" },
177122

178-
// TDP_RAM36K = 32,
123+
// TDP_RAM36K
179124
{ "RDATA_A", "RPARITY_A", "RDATA_B", "RPARITY_B" },
180125

181-
{}, // X_UNKNOWN = 33,
182-
{}, // Y_UPPER_GUARD = 34
126+
{}, // X_UNKNOWN
127+
{}, // Y_UPPER_GUARD
183128
{}
184-
};
129+
}; // _id2outputs
130+
131+
static vector<string> _id2clocks[] = {
132+
{}, // 0
133+
134+
{ "O" }, // BOOT_CLOCK
135+
{ }, // CARRY
136+
137+
{ "I", "O" }, // CLK_BUF
138+
139+
{ "C" }, // DFFNRE
140+
141+
{ "C" }, // DFFRE
142+
143+
{ "CLK" }, // DSP19X2
144+
145+
{ "CLK" }, // DSP38
146+
147+
// FIFO18KX2
148+
{ "WR_CLK1", "RD_CLK1",
149+
"WR_CLK2", "RD_CLK2" },
150+
151+
// FIFO36K
152+
{ "WR_CLK", "RD_CLK" },
153+
154+
{ }, // I_BUF
155+
{ }, // I_BUF_DS
156+
157+
{ "C" }, // I_DDR
158+
159+
{ "CLK_IN" }, // I_DELAY
160+
161+
{ }, // IO_BUF
162+
{ }, // IO_BUF_DS
163+
164+
// I_SERDES
165+
{ "CLK_IN", "CLK_OUT", "PLL_CLK" },
166+
167+
{ }, // LUT1
168+
{ }, // LUT2
169+
{ }, // LUT3
170+
{ }, // LUT4
171+
{ }, // LUT5
172+
{ }, // LUT6
173+
174+
{ }, // O_BUF
175+
{ }, // O_BUF_DS
176+
177+
{ }, // O_BUFT
178+
{ }, // O_BUFT_DS
179+
180+
{ }, // O_DDR
181+
182+
{ }, // O_DELAY
183+
184+
{ "CLK_IN", "PLL_CLK" }, // O_SERDES
185+
186+
{ "PLL_CLK" }, // O_SERDES_CLK
187+
188+
{ "CLK_OUT", "FAST_CLK" }, // PLL
189+
190+
// TDP_RAM18KX2
191+
{ "CLK_A1", "CLK_B1",
192+
"CLK_A2", "CLK_B2" },
193+
194+
// TDP_RAM36K
195+
{ "CLK_A", "CLK_B" },
196+
197+
{}, // X_UNKNOWN
198+
{}, // Y_UPPER_GUARD
199+
{}
200+
}; // _id2clocks
185201

186202
}
187203

@@ -202,6 +218,15 @@ bool prim_cpin_is_output(Prim_t primId, CStr pinName) noexcept {
202218
return _vec_contains(V, pinName);
203219
}
204220

221+
bool prim_cpin_is_clock(Prim_t primId, CStr pinName) noexcept {
222+
uint i = primId;
223+
assert(i <= Prim_MAX_ID);
224+
if (i == 0 or !pinName or !pinName[0] or i > Prim_MAX_ID)
225+
return false;
226+
const vector<string>& V = _id2clocks[i];
227+
return _vec_contains(V, pinName);
228+
}
229+
205230
CStr primt_name(Prim_t enu) noexcept {
206231
static_assert(sizeof(_enumNames) / sizeof(_enumNames[0]) == Y_UPPER_GUARD + 1);
207232
uint i = enu;
@@ -374,14 +399,10 @@ Prim_t primt_id(CStr name) noexcept {
374399
return Y_UPPER_GUARD;
375400
if (starts_w_A(name))
376401
return A_ZERO;
377-
378-
if (::strcmp(name, "CARRY") == 0) // TMP
379-
return CARRY_CHAIN;
380402
if (starts_w_CAR(name))
381-
return CARRY_CHAIN;
403+
return CARRY;
382404

383-
uint X = X_UNKNOWN;
384-
for (uint i = 1; i < X; i++) {
405+
for (uint i = 1; i < Prim_MAX_ID; i++) {
385406
if (::strcmp(_enumNames[i], name) == 0)
386407
return (Prim_t)i;
387408
}

0 commit comments

Comments
 (0)