RgGen
Users following rggen
Jung Jae Min
jmjung0
RTL(Verilog/System Verilog/VHDL)
FPGA(Xilinx, Altera)
Embedded SW (Linux/Yocto, C/C++)
Compute Accelerator HW
RISC-V
Ray Tracing
AI/ DeepLearning
SiliconArts Seoul
James
FPGA-James
FPGA Developer with 10 years experience
2 years ASIC experience.
This repo is for personal projects and configuration files I use for development
Pradeep Purushothaman Vadakkodathu
vadakkodan
SoC/FPGA IP Design Engineer | Verilog | VHDL | SystemVerilog | C | BASH | Python | Linux | XILINX | Intel Altera | ISE | Vivado | XPS | XSG |
Matlab | 5GNR
Freelancer Bengaluru
Konstantin Tiutin
MarsWise
Wireless Engineer | RF Engineer | SDR Engineer | DSP Engineer | Embedded Engineer | FPGA Engineer | Hardware Design Engineer | Electronics Design Engineer
Tbilisi
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