agra-uni-bremen

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60 repositories

fv-lidac
Public
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
Verilog
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Other
•0•1•0•0•Updated Jul 17, 2025Jul 17, 2025
opt-vp
Public
Virtual Prototype for identifying Application Specific Hardware Optimization candidates
C++
•
MIT License
•2•9•0•0•Updated Jul 10, 2025Jul 10, 2025
sefos
Public
SEFOS (Symbolic Execution For Original SystemC)
C++
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Other
•698•0•0•0•Updated Jun 12, 2025Jun 12, 2025
symsysc-experiments
Public
Experiments and DUTs for SymSysC repo
C++
•
MIT License
•1•0•0•0•Updated Jun 12, 2025Jun 12, 2025
CrosSym
Public
Cross-Level Symbolic Execution of SystemC Peripherals
C++
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MIT License
•3•0•0•0•Updated Jun 12, 2025Jun 12, 2025
SymSysC
Public
Symbolic Execution of SystemC TLM Peripherals
C++
•3•5•0•0•Updated Jun 11, 2025Jun 11, 2025
BinSym
Public
Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model
symbolic-execution riscv program-analysis riscv32
Haskell
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MIT License
•3•50•0•0•Updated May 26, 2025May 26, 2025
vpil-hw
Public
Hardware Description for VPiL (Virtual Prototype in the Loop)
Verilog
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MIT License
•0•1•0•0•Updated Feb 17, 2025Feb 17, 2025
virtual-bus
Public
Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)
C++
•0•0•1•0•Updated Dec 13, 2024Dec 13, 2024
riscv-vp
Public
RISC-V Virtual Prototype
simulator cpu riscv tlm systemc soc risc-v vp tlm2 system-c
C++
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MIT License
•68•174•11•3•Updated Dec 13, 2024Dec 13, 2024
microrv32
Public
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
cpu fpga vhdl riscv rtl verilog soc risc-v spinalhdl softcore
Scala
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MIT License
•6•50•0•1•Updated Oct 23, 2024Oct 23, 2024
SpinalAGRADemo
Public
SpinalHDL demo for AGRA
Scala
•0•0•0•0•Updated Aug 25, 2024Aug 25, 2024
libriscv
Public
Extensible implementation of the RISC-V ISA based on FreeMonads
simulation free-monads formal-specification riscv-v
Haskell
•
MIT License
•2•17•0•0•Updated Jul 10, 2024Jul 10, 2024
vlsid2024-inputaware-approxadders-magic
Public
0•0•0•0•Updated Jun 5, 2024Jun 5, 2024
guix-symex
Public
A Guix channel for reproducible symbolic execution research
reproducible-research symbolic-execution guix software-testing klee
Scheme
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GNU General Public License v3.0
•0•1•0•0•Updated May 31, 2024May 31, 2024
opt-seq
Public
An algorithm to merge RISC-V instruction sequences
asic embedded-systems risc-v virtual-prototyping hardware-optimization
C++
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MIT License
•0•2•0•0•Updated Mar 6, 2024Mar 6, 2024
vp-integration-tests
Public
Tests for peripherals and other utilities of the riscv-vp
C
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Other
•1•2•0•0•Updated Jan 10, 2024Jan 10, 2024
symex_processor_verification
Public
C++
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MIT License
•3•6•0•0•Updated Dec 6, 2023Dec 6, 2023
crave
Public
Constrained random stimuli generation for C++ and SystemC
constrained-random systemc
C++
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Other
•13•52•11•0•Updated Nov 29, 2023Nov 29, 2023
JxCDC2022-imagin-add
Public
MIT License
•0•0•0•0•Updated Oct 5, 2023Oct 5, 2023
symex-vp
Public
A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
symbolic-execution systemc risc-v klee concolic-execution riscv32 concolic-testing riscv
C++
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GNU General Public License v3.0
•5•25•0•0•Updated Oct 4, 2023Oct 4, 2023
tcasii2022-maradiv-lib
Public
MIT License
•0•0•0•0•Updated Oct 2, 2023Oct 2, 2023
newcas2023-magic-multiplier-lib
Public
MIT License
•0•0•0•0•Updated Aug 3, 2023Aug 3, 2023
icee2022-magic-adder-lib
Public
Artifacts of the paper: "Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-Based Memristor Design Style"
MIT License
•0•0•0•0•Updated Aug 3, 2023Aug 3, 2023
formal-iss
Public
Generate an ISS for riscv-vp from a formal LibRISCV ISA model
simulation code-generation risc-v formal-specification riscv32 unparser
Haskell
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MIT License
•1•3•0•0•Updated Jul 13, 2023Jul 13, 2023
spike-libriscv
Public
Spike RISC-V simulator but with a autogenerated LibRISCV backend
C
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Other
•1•0•0•0•Updated Jul 10, 2023Jul 10, 2023
libriscv-vp
Public
RISC-V Virtual Prototype with ISS generated from LibRISCV
C++
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MIT License
•1•0•0•0•Updated Jul 10, 2023Jul 10, 2023
clover
Public
A library for concolic execution of RV32 instruction set simulators
symbolic-execution risc-v klee concolic-testing
C++
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GNU General Public License v3.0
•1•2•0•0•Updated Jul 6, 2023Jul 6, 2023
virtual-breadboard
Public
Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes
C++
•2•11•5•0•Updated Jun 4, 2023Jun 4, 2023
sifive-hifive1
Public
This Repo contains documentation to the HiFive1 Board along with some example programs.
C
•2•3•0•0•Updated Apr 4, 2023Apr 4, 2023