Repositories list

• RISCuinho-NG

  Public
  O RISCuinho em sua primeira versão foi fruto do meu estudo sobre Verilog e foi feito todo com base em livros, já na versão NG, está todo sendo feito com o Inteligência Generativa Windsurf que usa chatGPT, Claude entre outros. O nosso objetivo é educacional, portanto visamos o ensino de FPGA e seus recursos do básico ao avançado.

  Verilog

  •

  Creative Commons Zero v1.0 Universal

  •0•0•0•0•Updated May 24, 2025May 24, 2025

• core

  Public
  **RISC**uinho - A scratch in the possibilities in the universe of microcontrollers

  verilogrisc-vrv32i

  BSD 3-Clause "New" or "Revised" License

  •4•22•0•0•Updated Oct 10, 2022Oct 10, 2022

• tang-nano-psram

  Public
  A test of the PSRAM on the Sipeed Tang Nano

  Verilog

  •1•0•0•0•Updated Dec 30, 2021Dec 30, 2021

• riscuinho.github.io

  Public
  A scratch on Microcontroller universe

  HTML

  •

  MIT License

  •0•1•0•0•Updated Dec 17, 2021Dec 17, 2021

• EquipoGraph_LIB

  Public
  C++

  •0•0•0•0•Updated Sep 7, 2021Sep 7, 2021

• SIMULinho

  Public
  Simulador integrado iVerilog com interface QT, permite visualizar internamente e controlar a simulação do RISCuinho usando iVerilog

  QMake

  •

  GNU General Public License v3.0

  •0•0•0•0•Updated Sep 2, 2021Sep 2, 2021

• magic_enum

  Public
  Static reflection for enums (to string, from string, iteration) for modern C++, work with any enum type without any macro or boilerplate code

  C++

  •

  MIT License

  •497•0•0•0•Updated Aug 9, 2021Aug 9, 2021

• exemplos

  Public
  Exemplos usados para teste do RISCuinho, os códigos são em assembly ou C/C++, detalhes podem ser obtidos no em https://riscuinho.github.io/categories/exemplos

  risc-v-assembly

  Assembly

  •

  Creative Commons Zero v1.0 Universal

  •0•0•0•0•Updated Aug 7, 2021Aug 7, 2021

• Digital

  Public
  A digital logic designer and circuit simulator.

  Java

  •

  GNU General Public License v3.0

  •503•0•0•0•Updated Aug 7, 2021Aug 7, 2021

• apicula

  Public
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  Python

  •

  MIT License

  •76•0•0•0•Updated Jul 22, 2021Jul 22, 2021

• nextpnr

  Public
  nextpnr portable FPGA place and route tool

  C++

  •

  ISC License

  •268•0•0•0•Updated Jul 21, 2021Jul 21, 2021

• yosys

  Public
  Yosys Open SYnthesis Suite

  C++

  •

  ISC License

  •976•0•0•0•Updated Jul 21, 2021Jul 21, 2021

• apio-examples

  Public
  🌱 Apio examples

  Verilog

  •

  GNU General Public License v2.0

  •26•0•0•0•Updated Jul 17, 2021Jul 17, 2021

• LibFPGA

  Public
  Minha biblioteca de módulos útil a qualquer projeto com FPGA, de PLL, Gerador de números pseudo aleatórios, controladores externos, entre outros.

  libraryfpgartos+ 1risc-v

  Verilog

  •

  GNU Lesser General Public License v2.1

  •1•2•0•0•Updated Jul 2, 2021Jul 2, 2021

• chocopy

  Public
  ChocoPy website

  HTML

  •1•0•0•0•Updated Jun 29, 2021Jun 29, 2021

• riscv-gnu-toolchain

  Public
  GNU toolchain for RISC-V, including GCC

  C

  •

  Other

  •1.3k•0•0•0•Updated Jun 26, 2021Jun 26, 2021

• emulsiV

  Public
  A visual simulator, criado por @guillaum Savaton, for teaching computer architecture using the RISC-V instruction set

  riscvrisc-vriscv-simulator+ 1riscv32im

  JavaScript

  •

  Mozilla Public License 2.0

  •59•0•0•0•Updated Jun 25, 2021Jun 25, 2021

• riscv-gcc

  Public
  GNU General Public License v2.0

  •277•0•0•0•Updated Jun 23, 2021Jun 23, 2021

• riscv-binutils-gdb

  Public
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

  C

  •

  GNU General Public License v2.0

  •237•0•0•0•Updated Jun 22, 2021Jun 22, 2021

• iverilog

  Public
  Icarus Verilog

  C++

  •

  GNU General Public License v2.0

  •563•0•0•0•Updated Jun 21, 2021Jun 21, 2021

• riscv-v-spec

  Public
  Working draft of the proposed RISC-V V vector extension

  Assembly

  •

  Creative Commons Attribution 4.0 International

  •282•0•0•0•Updated Jun 20, 2021Jun 20, 2021

• riscv-eabi-spec

  Public
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

  Creative Commons Attribution 4.0 International

  •5•0•0•0•Updated Jun 7, 2021Jun 7, 2021

• verilog_systemverilog.vim

  Public
  Verilog/SystemVerilog Syntax and Omni-completion

  Vim Script

  •93•0•0•0•Updated Apr 21, 2021Apr 21, 2021

• venus

  Public
  RISC-V instruction set simulator built for education

  risc-vvenus

  MIT License

  •63•0•0•0•Updated Apr 21, 2021Apr 21, 2021

• riscv-formal

  Public
  RISC-V Formal Verification Framework

  Verilog

  •

  ISC License

  •33•0•0•0•Updated Mar 11, 2021Mar 11, 2021

• awesome-fpga-boards

  Public
  Second life for FPGA boards which can be repurposed to DYI/Hobby projects

  12•1•0•0•Updated Jan 12, 2021Jan 12, 2021

• gowin-easy-linux

  Public
  Easy setup of GoWin FPGA SDK on Linux. A single script (main_launcher) automates all the critical steps and quickly fires up the IDE.

  V

  •

  MIT License

  •7•0•0•0•Updated Apr 23, 2020Apr 23, 2020

• verilog-support

  Public
  Edit SystemVerilog files (and UVM files) in Vim/gVim

  Vim Script

  •5•0•0•0•Updated Nov 11, 2019Nov 11, 2019

• arachne-pnr

  Public
  Place and route tool for FPGAs

  C++

  •

  MIT License

  •72•0•0•0•Updated Jul 28, 2019Jul 28, 2019