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Hamlin Li
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8352504: RISC-V: implement and enable CMoveI/L
8346786: RISC-V: Reconsider ConditionalMoveLimit when adding conditional move Reviewed-by: fyang, fjiang
1 parent 50358d1 commit bcc33d5

20 files changed

+940
-49
lines changed

‎src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2156,6 +2156,36 @@ void C2_MacroAssembler::enc_cmove(int cmpFlag, Register op1, Register op2, Regis
21562156
}
21572157
}
21582158

2159+
void C2_MacroAssembler::enc_cmove_cmp_fp(int cmpFlag, FloatRegister op1, FloatRegister op2, Register dst, Register src, bool is_single) {
2160+
int op_select = cmpFlag & (~unsigned_branch_mask);
2161+
2162+
switch (op_select) {
2163+
case BoolTest::eq:
2164+
cmov_cmp_fp_eq(op1, op2, dst, src, is_single);
2165+
break;
2166+
case BoolTest::ne:
2167+
cmov_cmp_fp_ne(op1, op2, dst, src, is_single);
2168+
break;
2169+
case BoolTest::le:
2170+
cmov_cmp_fp_le(op1, op2, dst, src, is_single);
2171+
break;
2172+
case BoolTest::ge:
2173+
assert(false, "Should go to BoolTest::le case");
2174+
ShouldNotReachHere();
2175+
break;
2176+
case BoolTest::lt:
2177+
cmov_cmp_fp_lt(op1, op2, dst, src, is_single);
2178+
break;
2179+
case BoolTest::gt:
2180+
assert(false, "Should go to BoolTest::lt case");
2181+
ShouldNotReachHere();
2182+
break;
2183+
default:
2184+
assert(false, "unsupported compare condition");
2185+
ShouldNotReachHere();
2186+
}
2187+
}
2188+
21592189
// Set dst to NaN if any NaN input.
21602190
void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
21612191
FLOAT_TYPE ft, bool is_min) {

‎src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,10 @@
129129
Register op1, Register op2,
130130
Register dst, Register src);
131131

132+
void enc_cmove_cmp_fp(int cmpFlag,
133+
FloatRegister op1, FloatRegister op2,
134+
Register dst, Register src, bool is_single);
135+
132136
void spill(Register r, bool is64, int offset) {
133137
is64 ? sd(r, Address(sp, offset))
134138
: sw(r, Address(sp, offset));

‎src/hotspot/cpu/riscv/c2_globals_riscv.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ define_pd_global(bool, TieredCompilation, COMPILER1_PRESENT(true) NOT
4343
define_pd_global(intx, CompileThreshold, 10000);
4444

4545
define_pd_global(intx, OnStackReplacePercentage, 140);
46-
define_pd_global(intx, ConditionalMoveLimit, 0);
46+
define_pd_global(intx, ConditionalMoveLimit, 3);
4747
define_pd_global(intx, FreqInlineSize, 325);
4848
define_pd_global(intx, MinJumpTableSize, 10);
4949
define_pd_global(intx, InteriorEntryAlignment, 16);

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1267,6 +1267,130 @@ void MacroAssembler::cmov_gtu(Register cmp1, Register cmp2, Register dst, Regist
12671267
bind(no_set);
12681268
}
12691269

1270+
// ----------- cmove, compare float -----------
1271+
1272+
// Move src to dst only if cmp1 == cmp2,
1273+
// otherwise leave dst unchanged, including the case where one of them is NaN.
1274+
// Clarification:
1275+
// java code : cmp1 != cmp2 ? dst : src
1276+
// transformed to : CMove dst, (cmp1 eq cmp2), dst, src
1277+
void MacroAssembler::cmov_cmp_fp_eq(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single) {
1278+
if (UseZicond) {
1279+
if (is_single) {
1280+
feq_s(t0, cmp1, cmp2);
1281+
} else {
1282+
feq_d(t0, cmp1, cmp2);
1283+
}
1284+
czero_nez(dst, dst, t0);
1285+
czero_eqz(t0 , src, t0);
1286+
orr(dst, dst, t0);
1287+
return;
1288+
}
1289+
Label no_set;
1290+
if (is_single) {
1291+
// jump if cmp1 != cmp2, including the case of NaN
1292+
// not jump (i.e. move src to dst) if cmp1 == cmp2
1293+
float_bne(cmp1, cmp2, no_set);
1294+
} else {
1295+
double_bne(cmp1, cmp2, no_set);
1296+
}
1297+
mv(dst, src);
1298+
bind(no_set);
1299+
}
1300+
1301+
// Keep dst unchanged only if cmp1 == cmp2,
1302+
// otherwise move src to dst, including the case where one of them is NaN.
1303+
// Clarification:
1304+
// java code : cmp1 == cmp2 ? dst : src
1305+
// transformed to : CMove dst, (cmp1 ne cmp2), dst, src
1306+
void MacroAssembler::cmov_cmp_fp_ne(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single) {
1307+
if (UseZicond) {
1308+
if (is_single) {
1309+
feq_s(t0, cmp1, cmp2);
1310+
} else {
1311+
feq_d(t0, cmp1, cmp2);
1312+
}
1313+
czero_eqz(dst, dst, t0);
1314+
czero_nez(t0 , src, t0);
1315+
orr(dst, dst, t0);
1316+
return;
1317+
}
1318+
Label no_set;
1319+
if (is_single) {
1320+
// jump if cmp1 == cmp2
1321+
// not jump (i.e. move src to dst) if cmp1 != cmp2, including the case of NaN
1322+
float_beq(cmp1, cmp2, no_set);
1323+
} else {
1324+
double_beq(cmp1, cmp2, no_set);
1325+
}
1326+
mv(dst, src);
1327+
bind(no_set);
1328+
}
1329+
1330+
// When cmp1 <= cmp2 or any of them is NaN then dst = src, otherwise, dst = dst
1331+
// Clarification
1332+
// scenario 1:
1333+
// java code : cmp2 < cmp1 ? dst : src
1334+
// transformed to : CMove dst, (cmp1 le cmp2), dst, src
1335+
// scenario 2:
1336+
// java code : cmp1 > cmp2 ? dst : src
1337+
// transformed to : CMove dst, (cmp1 le cmp2), dst, src
1338+
void MacroAssembler::cmov_cmp_fp_le(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single) {
1339+
if (UseZicond) {
1340+
if (is_single) {
1341+
flt_s(t0, cmp2, cmp1);
1342+
} else {
1343+
flt_d(t0, cmp2, cmp1);
1344+
}
1345+
czero_eqz(dst, dst, t0);
1346+
czero_nez(t0 , src, t0);
1347+
orr(dst, dst, t0);
1348+
return;
1349+
}
1350+
Label no_set;
1351+
if (is_single) {
1352+
// jump if cmp1 > cmp2
1353+
// not jump (i.e. move src to dst) if cmp1 <= cmp2 or either is NaN
1354+
float_bgt(cmp1, cmp2, no_set);
1355+
} else {
1356+
double_bgt(cmp1, cmp2, no_set);
1357+
}
1358+
mv(dst, src);
1359+
bind(no_set);
1360+
}
1361+
1362+
// When cmp1 < cmp2 or any of them is NaN then dst = src, otherwise, dst = dst
1363+
// Clarification
1364+
// scenario 1:
1365+
// java code : cmp2 <= cmp1 ? dst : src
1366+
// transformed to : CMove dst, (cmp1 lt cmp2), dst, src
1367+
// scenario 2:
1368+
// java code : cmp1 >= cmp2 ? dst : src
1369+
// transformed to : CMove dst, (cmp1 lt cmp2), dst, src
1370+
void MacroAssembler::cmov_cmp_fp_lt(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single) {
1371+
if (UseZicond) {
1372+
if (is_single) {
1373+
fle_s(t0, cmp2, cmp1);
1374+
} else {
1375+
fle_d(t0, cmp2, cmp1);
1376+
}
1377+
czero_eqz(dst, dst, t0);
1378+
czero_nez(t0 , src, t0);
1379+
orr(dst, dst, t0);
1380+
return;
1381+
}
1382+
Label no_set;
1383+
if (is_single) {
1384+
// jump if cmp1 >= cmp2
1385+
// not jump (i.e. move src to dst) if cmp1 < cmp2 or either is NaN
1386+
float_bge(cmp1, cmp2, no_set);
1387+
} else {
1388+
double_bge(cmp1, cmp2, no_set);
1389+
}
1390+
mv(dst, src);
1391+
bind(no_set);
1392+
}
1393+
12701394
// Float compare branch instructions
12711395

12721396
#define INSN(NAME, FLOATCMP, BRANCH) \

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -657,6 +657,11 @@ class MacroAssembler: public Assembler {
657657
void cmov_gt(Register cmp1, Register cmp2, Register dst, Register src);
658658
void cmov_gtu(Register cmp1, Register cmp2, Register dst, Register src);
659659

660+
void cmov_cmp_fp_eq(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
661+
void cmov_cmp_fp_ne(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
662+
void cmov_cmp_fp_le(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
663+
void cmov_cmp_fp_lt(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
664+
660665
public:
661666
// We try to follow risc-v asm menomics.
662667
// But as we don't layout a reachable GOT,

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