8361353: [PPC64] C2: Add nodes UMulHiL, CmpUL3, UMinV, UMaxV, NegVI

dbriemann · TheRealMDoerr · commit 5c67e3d6e573 · 2025-07-08T12:58:44.000Z
Reviewed-by: mdoerr, rrich
diff --git a/src/hotspot/cpu/ppc/assembler_ppc.hpp b/src/hotspot/cpu/ppc/assembler_ppc.hpp
@@ -757,6 +757,7 @@ class Assembler : public AbstractAssembler {
     VCTZH_OPCODE   = (4u  << OPCODE_SHIFT | 29u << 16 | 1538u),
     VCTZW_OPCODE   = (4u  << OPCODE_SHIFT | 30u << 16 | 1538u),
     VCTZD_OPCODE   = (4u  << OPCODE_SHIFT | 31u << 16 | 1538u),
+    VNEGW_OPCODE   = (4u  << OPCODE_SHIFT |  6u << 16 | 1538u),
 
     // Vector Floating-Point
     // not implemented yet
@@ -2372,6 +2373,7 @@ class Assembler : public AbstractAssembler {
   inline void vctzh(    VectorRegister d, VectorRegister b);
   inline void vctzw(    VectorRegister d, VectorRegister b);
   inline void vctzd(    VectorRegister d, VectorRegister b);
+  inline void vnegw(    VectorRegister d, VectorRegister b);
   // Vector Floating-Point not implemented yet
   inline void mtvscr(   VectorRegister b);
   inline void mfvscr(   VectorRegister d);
diff --git a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
@@ -1092,6 +1092,9 @@ inline void Assembler::vctzd(   VectorRegister d, VectorRegister b)
 inline void Assembler::mtvscr(  VectorRegister b)                                     { emit_int32( MTVSCR_OPCODE   | vrb(b)); }
 inline void Assembler::mfvscr(  VectorRegister d)                                     { emit_int32( MFVSCR_OPCODE   | vrt(d)); }
 
+// Vector Negate Word (introduced with Power 9)
+inline void Assembler::vnegw(   VectorRegister d, VectorRegister b)                   { emit_int32( VNEGW_OPCODE    | vrt(d) | vrb(b)); }
+
 // AES (introduced with Power 8)
 inline void Assembler::vcipher(     VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHER_OPCODE      | vrt(d) | vra(a) | vrb(b)); }
 inline void Assembler::vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHERLAST_OPCODE  | vrt(d) | vra(a) | vrb(b)); }
diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad
@@ -2193,6 +2193,7 @@ bool Matcher::match_rule_supported(int opcode) {
     case Op_DivVD:
     case Op_AbsVF:
     case Op_AbsVD:
+    case Op_NegVI:
     case Op_NegVF:
     case Op_NegVD:
     case Op_SqrtVF:
@@ -2203,6 +2204,8 @@ bool Matcher::match_rule_supported(int opcode) {
     case Op_RoundDoubleModeV:
     case Op_MinV:
     case Op_MaxV:
+    case Op_UMinV:
+    case Op_UMaxV:
     case Op_AndV:
     case Op_OrV:
     case Op_XorV:
@@ -2268,7 +2271,11 @@ bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
     // MaxV, MinV need types == INT || LONG.
     case Op_MaxV:
     case Op_MinV:
+    case Op_UMinV:
+    case Op_UMaxV:
       return bt == T_INT || bt == T_LONG;
+    case Op_NegVI:
+      return PowerArchitecturePPC64 >= 9 && bt == T_INT;
   }
   return true; // Per default match rules are supported.
 }
@@ -8422,6 +8429,18 @@ instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct uMulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
+  match(Set dst (UMulHiL src1 src2));
+  ins_cost(DEFAULT_COST);
+
+  format %{ "MULHDU   $dst $src1, $src2 \t// unsigned long" %}
+  size(4);
+  ins_encode %{
+    __ mulhdu($dst$$Register, $src1$$Register, $src2$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // Immediate Multiplication
 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
   match(Set dst (MulL src1 src2));
@@ -10783,6 +10802,36 @@ instruct cmpL3_reg_reg(iRegIdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 c
   ins_pipe(pipe_class_default);
 %}
 
+instruct cmpU3_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
+  match(Set dst (CmpU3 src1 src2));
+  effect(KILL cr0);
+  ins_cost(DEFAULT_COST * 5);
+  size((VM_Version::has_brw() ? 16 : 20));
+
+  format %{ "cmpU3_reg_reg $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ cmplw(CR0, $src1$$Register, $src2$$Register);
+    __ set_cmp3($dst$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct cmpUL3_reg_reg(iRegIdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
+  match(Set dst (CmpUL3 src1 src2));
+  effect(KILL cr0);
+  ins_cost(DEFAULT_COST * 5);
+  size((VM_Version::has_brw() ? 16 : 20));
+
+  format %{ "cmpUL3_reg_reg $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ cmpld(CR0, $src1$$Register, $src2$$Register);
+    __ set_cmp3($dst$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // Implicit range checks.
 // A range check in the ideal world has one of the following shapes:
 //  - (If le (CmpU length index)), (IfTrue  throw exception)
@@ -13347,6 +13396,46 @@ instruct vmax_reg(vecX dst, vecX src1, vecX src2) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct vminu_reg(vecX dst, vecX src1, vecX src2) %{
+  match(Set dst (UMinV src1 src2));
+  format %{ "VMINU  $dst,$src1,$src2\t// vector unsigned min" %}
+  size(4);
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    switch (bt) {
+      case T_INT:
+        __ vminuw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
+        break;
+      case T_LONG:
+        __ vminud($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
+        break;
+      default:
+        ShouldNotReachHere();
+    }
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct vmaxu_reg(vecX dst, vecX src1, vecX src2) %{
+  match(Set dst (UMaxV src1 src2));
+  format %{ "VMAXU  $dst,$src1,$src2\t// vector unsigned max" %}
+  size(4);
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    switch (bt) {
+      case T_INT:
+        __ vmaxuw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
+        break;
+      case T_LONG:
+        __ vmaxud($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
+        break;
+      default:
+        ShouldNotReachHere();
+    }
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 instruct vand(vecX dst, vecX src1, vecX src2) %{
   match(Set dst (AndV src1 src2));
   size(4);
@@ -13507,6 +13596,17 @@ instruct vneg2D_reg(vecX dst, vecX src) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct vneg4I_reg(vecX dst, vecX src) %{
+  match(Set dst (NegVI src));
+  predicate(PowerArchitecturePPC64 >= 9 && Matcher::vector_element_basic_type(n) == T_INT);
+  format %{ "VNEGW $dst,$src\t// negate int vector" %}
+  size(4);
+  ins_encode %{
+    __ vnegw($dst$$VectorRegister, $src$$VectorRegister);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // Vector Square Root Instructions
 
 instruct vsqrt4F_reg(vecX dst, vecX src) %{
diff --git a/test/hotspot/jtreg/compiler/intrinsics/TestCompareUnsigned.java b/test/hotspot/jtreg/compiler/intrinsics/TestCompareUnsigned.java
@@ -30,7 +30,8 @@
  * @test
  * @key randomness
  * @bug 8283726 8287925
- * @requires os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64" | os.arch=="riscv64"
+ * @requires os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64" | os.arch=="riscv64" | os.arch=="ppc64" | os.arch=="ppc64le"
+
  * @summary Test the intrinsics implementation of Integer/Long::compareUnsigned
  * @library /test/lib /
  * @run driver compiler.intrinsics.TestCompareUnsigned
