genesys2 synthesis not working #1490
Description
Hi there,
I'm trying to do the synthesis for genesys2 board like this:
/fpga/generator$ make genesys2
This gives the following errors:
INFO: [Synth 8-11241] undeclared symbol 'ahblite_resetn', assumed default net type 'wire' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:212]
INFO: [Synth 8-11241] undeclared symbol 'cpu_reset', assumed default net type 'wire' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:213]
INFO: [Synth 8-11241] undeclared symbol 'calib', assumed default net type 'wire' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:214]
INFO: [Synth 8-11241] undeclared symbol 'phy_rx_dv', assumed default net type 'wire' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:597]
INFO: [Synth 8-11241] undeclared symbol 'phy_rx_er', assumed default net type 'wire' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:598]
INFO: [Synth 8-6157] synthesizing module 'fpgaTop' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:31]
INFO: [Synth 8-6157] synthesizing module 'mmcm' [/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/mmcm_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'mmcm' (0#1) [/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/mmcm_stub.v:6]
ERROR: [Synth 8-11365] for the instance 'mmcm' of module 'mmcm' declared at '/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/mmcm_stub.v:6', named port connection 'clk_in1_p' does not exist [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:233]
ERROR: [Synth 8-11365] for the instance 'mmcm' of module 'mmcm' declared at '/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/mmcm_stub.v:6', named port connection 'clk_in1_n' does not exist [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:234]
INFO: [Synth 8-6157] synthesizing module 'sysrst' [/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/sysrst_stub.v:6]
ERROR: [Synth 8-6156] failed synthesizing module 'sysrst' [/yocto/fpga/cvw/fpga/generator/WallyFPGA.runs/synth_1/.Xil/Vivado-2090270-juan-Vivobook-ASUSLaptop-X1605VA-X1605VA/realtime/sysrst_stub.v:6]
ERROR: [Synth 8-6156] failed synthesizing module 'fpgaTop' [/yocto/fpga/cvw/fpga/src/fpgaTopGenesys2.sv:31]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2196.000 ; gain = 539.766 ; free physical = 6204 ; free virtual = 15283
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
20 Infos, 30 Warnings, 1 Critical Warnings and 5 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Tue Jul 22 12:40:13 2025...
[Tue Jul 22 12:40:16 2025] synth_1 finished
ERROR: [Vivado 12-13638] Failed runs(s) : 'synth_1'
wait_on_runs: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 1493.656 ; gain = 0.000 ; free physical = 7609 ; free virtual = 16694
ERROR: [Common 17-39] 'wait_on_runs' failed due to earlier errors.
while executing
"wait_on_run synth_1"
(file "wally.tcl" line 86)
Vivado%
The Genesys 2 board has been integrated recently. Is this supposed to be working already?
I'm using Ubuntu 22.04 and Vivado 2024.2
Synthesis for 'artya7' target finishes without issues.
Thanks