🔖 Release 0.5.4

Author: Stefan Mach

Bender.yml

@@ -3,8 +3,8 @@ package:
   authors: ["Stefan Mach <smach@iis.ee.ethz.ch>"]
 
 dependencies:
-  common_cells: {git: "https://github.com/pulp-platform/common_cells.git", rev: 32dd115}
-  fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", rev: e10ab86}
+  common_cells: {git: "https://github.com/pulp-platform/common_cells.git",         version: v1.13.1}
+  fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", version: v1.0.1}
 
 sources:
   - src/fpnew_pkg.sv

README.md

@@ -30,6 +30,8 @@ Multiple integer formats with arbitrary number of bits (as source or destionatio
 - Conversions between FP formats and integers (signed & unsigned) and vice versa
 - Classification
 
+Multi-format FMA operations (i.e. multiplication in one format, accumulation in another) are optionally supported. 
+
 Optionally, *packed-SIMD* versions of all the above operations can be generated for formats narrower than the FPU datapath width.
 E.g.: Support for double-precision (64bit) operations and two simultaneous single-precision (32bit) operations.
 

docs/CHANGELOG.md

@@ -5,23 +5,42 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
 In this sense, we interpret the "Public API" of a hardware module as its port/parameter list.
+Versions of the IP in the same major relase are "pin-compatible" with each other. Minor relases are permitted to add new parameters as long as their default bindings ensure backwards compatibility.
 
 
 ## [Unreleased]
 ### Added
 ### Changed
 ### Fixed
 
+
+## [0.5.4] - 2019-06-02
+
+### Added
+- Documentation about multi-format operations
+- Extended pipelining description slightly
+- Extended semantic versioning declaration in changelog
+
+### Changed
+- Updated diagrams in architecture documentation
+
+### Fixed
+- [common_cells] Bumped to fix src_files.yml bugs
+- [fpu_div_sqrt_mvp] Bumped to fix linter warnings
+
+
 ## [0.5.3] - 2019-05-31
 
 ### Fixed
 - ips_list.yml entry for updated common_cells
 
+
 ## [0.5.2] - 2019-05-31
 
 ### Fixed
 - Internal pipeline bypass in cast unit
 
+
 ## [0.5.1] - 2019-05-27
 
 ### Fixed

docs/README.md

@@ -427,6 +427,8 @@ Results from all lanes are collected and assembled at the output of the slice.
 
 Implementing units as merged slices usually yields best total area, however costs more in terms of per-format latency.
 
+When the `ADDMUL` block is implemented using the `MERGED` implementation, multi-format FMA (multiplication done in `src_format`, accumulation in `dst_format`) is automatically supported among all formats using `MERGED`.
+
 ![FPnew](fig/multislice_block.png)
 
 
@@ -436,6 +438,9 @@ Pipeline registers are inserted into the operational units directly, according t
 As such, each slice in the system can have a different latency.
 Merged slices are bound to thave the largest latency of the included formats.
 
+All pipeline registers are inserted as shift registers at predefined locations in the FPU.
+For optimal mapping, retiming funcitonality of your synthesis tools should be used to balance the paths between registers.
+
 Data traverses the pipeline stages within the operational units using the same handshaking mechanism that is also present at the top-level FPU interface.
 An individual pipeline stage is only stalled if its successor stage is stalled and cannot proceed in the following cycle.
 In general, different operations can overtake each other in the FPU if their latencies differ or significant backpressure exists in one of the paths.

docs/fig/multislice_block.png

@@ -19,9 +19,9 @@
 #
 
 common_cells:
-  commit: 0b8c10c21c9f810509bbd7bf86cfbdc4e6626c8e
+  commit: v1.13.1
   domain: [soc, cluster]
 
 fpu_div_sqrt_mvp:
-  commit: master
+  commit: v1.0.1
   domain: [cluster,soc]