📚 Bump version to 0.6.0

Author: Stefan Mach

docs/CHANGELOG.md

@@ -11,6 +11,11 @@ Versions of the IP in the same major relase are "pin-compatible" with each other
 ## [Unreleased]
 
 ### Added
+### Changed
+### Fixed
+
+## [0.6.0] - 2019-07-04
+
 ### Changed
 - Pipelines are generated in the datapath modules instead of separate instances
 
@@ -21,12 +26,14 @@ Versions of the IP in the same major relase are "pin-compatible" with each other
 - Generation of merged slices when the first package format is disabled
 - Potential simulation/synthesis mismatch of the UF flag
 - Various linter warnings
+- Documentation to reflect on updated pipeline distribution order
 - [fpu_div_sqrt_mvp] Bumped to fix linter warnings
 - [Bender] Fixed dependencies for Bender [(#14)](https://github.com/pulp-platform/fpnew/pull/15)
 
 ### Removed
 - Currently unused modules: `fpnew_pipe*`, `fpnew_{f2i,f2f,i2f}_cast`
 
+
 ## [0.5.6] - 2019-06-12
 
 ### Changed

docs/README.md

@@ -336,12 +336,12 @@ For best results, we *strongly* encourage the use of automatic retiming options
 
 The configuration  `pipe_config_t` is an enumeration of type `logic [1:0]` holding the following implementation options for the pipelines in operational units:
 
-|   Enumerator  |                                             Description                                             |
-|---------------|-----------------------------------------------------------------------------------------------------|
-| `BEFORE`      | All pipeline registers are inserted at the inputs of the operational unit                           |
-| `AFTER`       | All pipeline registers are inserted at the outputs of the operational unit                          |
-| `INSIDE`      | All registers are inserted at roughly the middle of the operational unit (if not possible, `AFTER`) |
-| `DISTRIBUTED` | Registers are evenly distributed to `INSIDE`, `AFTER`, and `BEFORE` (if no `INSIDE`, all `AFTER`)   |
+|   Enumerator  |                                             Description                                              |
+|---------------|------------------------------------------------------------------------------------------------------|
+| `BEFORE`      | All pipeline registers are inserted at the inputs of the operational unit                            |
+| `AFTER`       | All pipeline registers are inserted at the outputs of the operational unit                           |
+| `INSIDE`      | All registers are inserted at roughly the middle of the operational unit (if not possible, `BEFORE`) |
+| `DISTRIBUTED` | Registers are evenly distributed to `INSIDE`, `BEFORE`, and `AFTER` (if no `INSIDE`, all `BEFORE`)   |