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Technically yes, if CVA6 would make use of AXI4 features (multiple beats, sub-bus size accesses). It is a bit hacky as it is, but CVA6 does not perform such accesses on the memory region of the CLINT. We do have an |
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Hi, All
I found the ariane_testharness.sv is conneting the clint to a AXI4 xbar, while clint is only a AXI4 lite interface.
Is there any design risk to doing this?
Thanks
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