Use access fault exceptions for non naturally aligned LR/SC and AMOs

[Silabs-ArjanB]

For LR, SC and AMOs the CV32E40X currently generates address-misaligned exceptions in case of usage of non naturally aligned addresses. These exceptions should be changed into access fault exceptions instead.

The following changes are required:

1. Usage of "exception code 4 Load address misaligned" needs to be changed to "exception code 5 Load access fault"
2. Usage of "exception code 6 Store/AMO address misaligned" needs to be changed to "exception code 7 Store/AMO access fault"
3. etrigger shall no longer support matching for exception codes 4 and 6 (bit 4 and 6 of tdta2 when tdata1.TYPE = 0x5 become WARL 0x0)
4. RVFI formats need to be updated (cause_type will change for all access faults reasons)
5. https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/exceptions_interrupts.html#exceptions needs to be updated
6. https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/control_status_registers.html#trigger-data-register-2-tdata2-view-when-tdata1-type-is-0x5 needs to be updated
7. table 26 of https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/rvfi.html# needs to be updated

[Silabs-ArjanB]

RTL was already fixed in #976.

Documentation updates and RVFI correction remain.