Related to timing constraints in CV32E40P #1048
Description
Design details: CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform.
Link : https://github.com/openhwgroup/cv32e40p
I would like to know if there is any false path and multiple cycle paths in this design?
I got some infeasible paths warning during synthesis, I checked the constraints file in the link given above but it seems there are no such paths. If anyone knows anything about this design please guide me.
Thanks in advance.