Linting Warnings in CV32E40P ASIC Implementation (DC Compiler)

[ahmd-kamel]

During ASIC implementation of the CV32E40P core using Synopsys Design Compiler (DC), several linting warnings were observed. While the core passes Formality checks, these warnings may indicate potential issues or areas for optimization. Below is a summary of the warnings for further investigation.

Linting Warnings:

LINT-2: Unloaded net apu_flags[0] in cv32e40p_top.

LINT-6: Input port fetch_enable_i drives wired logic (possible incorrect direction).

LINT-28: Unconnected port pulp_clock_en_i in cv32e40p_sleep_unit.

LINT-29: Direct input-to-output connection (trans_addr_i[31] → obi_addr_o[31]).

LINT-31: Direct output-to-output connection (fpu_fflags_we_o → apu_req_o).

LINT-32: Submodule core_i pin tied to logic 0/1.

LINT-33: Shared net driving multiple pins on core_i.

LINT-34: Non-tri-state driver on a tri-state bus (Logic0).

LINT-52: Output port apu_read_regs_o[2][4] tied to logic 0.

LINT-54: Multiply-driven net Logic0 (constant 0).

Questions:

• Are these warnings expected behavior so I can waive them ?
• Should any of these be addressed for robustness or synthesis optimization?

[MikeOpenHWGroup]

Hi @ahmd-kamel, thanks for your interest in the CV32E40P. For the latest version of this core (v1.8.3), you can find the list of waived lint warnings in Issue #670. Note that Questa 2022.4 was the lint tool used, and results with DC may be different.

Also, please note that we have not fully verified every possible configuration of this core (yet). Have a look at the User Manual for details about that.