RTL Code Coverage Hole in cv32e40p_EX_stage module line 237 and 241 #1023
Description
Component
Component:RTL
Issue Description
One of the possible combination in the if statements line 237 and 241 of cv32e40p_EX_stage was not covered during all the simulation non-regressions for 0 cycle latency and 2 cycle latency on the FPU.
After analysis we suspected that this scenario was in fact unreachable as in those configurations all FPU instructions are either single_cycle or multi_cycle (ie more than 1 cycle)
Siemens Questa Static formal tool was used to prove that this scenario was unreachable. For this scenario a dedicated assertion was written, named assert_unreachable_ex_237.
All information necessary to reproduce and analyze our work with formal can be found in the ReadMe in the cv32e40p/scripts/formal folder
As it was too late to implement a fix in the RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive this scenario hole in v2.
