RTL code coverage hole in CV32E40P lzc #1022
Description
Component
Component:RTL
Issue Description
The interconnect between the core and the FPU has been designed to handle multiple cores to multiple FPU connections. As the verification has been done with a one-core setup, the LZC used to arbitrate between different core is under-utilized and some part of the code is unreachable in this setup.
As it was too late to implement a different solution in RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive those holes in v2.