Builtin optimisation enhancement #22
Description
The CORE-V builtins can be enhanced by expanding the rtl for each instruction. This would allow gcc to pattern match to these builtins.
More testing with a simulator would be required.
Added, untested with simulator:
- XCVmac
- XCValu
- XCVelw
- XCVbi
- XCVmem
- XCVbitmanip
- XCVsimd
- XCVhwlp