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CV32E40P/dev: uvmt generic_exception_test does not work with DSim #2636

@djvra

Description

@djvra

DSim 2025.1 on Ubuntu 24.04 LTS, Windows 11 WSL
command: make test TEST=generic_exception_test SIMULATOR=dsim USE_ISS=0
I'm really sorry for the weird formatting below, I don't know how to fix it...

UVM_INFO @ 0.000 ns : uvmt_cv32e40p_base_test.sv(260) uvm_test_top [BASE TEST] Testcase configuration:
------------------------------------------------------------------------------------
Name                        Type                      Size  Value
------------------------------------------------------------------------------------
test_cfg                    uvmt_cv32e40p_test_cfg_c  -     @724
  heartbeat_period          integral                  32    'h30d40
  watchdog_timeout          integral                  32    'h5f5e100
  tpt                       test_program_type         32    PREEXISTING_SELFCHECKING
  run_riscv_gcc_toolchain   integral                  1     'h1
  print_uvm_runflow_banner  integral                  1     'h0
------------------------------------------------------------------------------------

UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000000
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000004
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000008
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x1000000c
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000010
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000014
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000018
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x1000001c
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000020
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000024
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_virtual_printer, addr: 0x10000028
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_cycle_counter, addr: 0x15001004
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_cycle_counter, addr: 0x15001008
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_rand_num, addr: 0x15001000
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_sig_writer, addr: 0x20000008
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_sig_writer, addr: 0x2000000c
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_sig_writer, addr: 0x20000010
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_status_flags, addr: 0x20000000
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_status_flags, addr: 0x20000004
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_interrupt_timer, addr: 0x15000000
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_interrupt_timer, addr: 0x15000004
UVM_INFO @ 0.000 ns : uvme_cv32e40p_env.sv(292) uvm_test_top.env [CV32E40PVPSEQ] Able to cast vp_interrupt_timer correctly.
UVM_INFO @ 0.000 ns : uvma_obi_memory_slv_seq.sv(207) reporter@@data_slv_seq [OBIVPSEQ] Virtual register: vp_debug_control, addr: 0x15000008
[CORE_TRACER  x] Output filename is: trace_core_xxxxxxxx.log
UVM_INFO @ 0.000 ns : uvme_cv32e40p_core_cntrl_fetch_toggle_seq.sv(76) uvm_test_top.env.core_cntrl_agent.sequencer@@fetch_toggle_seq [FETCHTOGGLE] Driving fetch_en with mode: FETCH_INITIAL_DELAY_CONSTANT
UVM_INFO @ 0.000 ns : uvml_mem.sv(104) reporter [MEMREADMEMH] Loading memory contents from /home/e/core-v-verif/cv32e40p/sim/uvmt/dsim_results/default/generic_exception_test/0/test_program/generic_exception_test.hex
UVM_INFO @ 0.000 ns : uvme_cv32e40p_vp_sig_writer_seq.sv(62) uvm_test_top.env.obi_memory_data_agent.sequencer@@data_slv_seq.vp_sig_writer [E40PVPSTATUS] cv32e40p_cntxt initialized in virtual peripheral
UVM_INFO @ 0.000 ns : uvmt_cv32e40p_base_test.sv(282) uvm_test_top [BASE TEST] Starting reset virtual sequence:
----------------------------------------------------------------
Name                    Type                        Size  Value
----------------------------------------------------------------
reset_vseq              uvme_cv32e40p_reset_vseq_c  -     @710
  num_clk_before_reset  integral                    32    'd50
  rst_deassert_period   integral                    32    'd7400
  post_rst_wait         integral                    32    'd7400
  req                   object                      -     <null>
  rsp                   object                      -     <null>
----------------------------------------------------------------

=E:[UpViolation] unique case violation at /home/e/core-v-verif/core-v-cores/cv32e40p/rtl/cv32e40p_load_store_unit.sv:419:5
  Time: 0.000 ns
  Instance: uvmt_cv32e40p_tb.dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i
  No item hit.
UVM_INFO @ 2.000 ns : uvme_cv32e40p_reset_vseq.sv(76) uvm_test_top.env.vsequencer@@reset_vseq [RST_VSEQ] Asserting reset for 7.400 ns
UVM_INFO @ 2.000 ns : uvma_clknrst_drv.sv(161) uvm_test_top.env.clknrst_agent.driver [CLKNRST] Asserting reset for 7.400 ns
UVM_INFO @ 2.000 ns : uvma_obi_memory_mon.sv(178) uvm_test_top.env.obi_memory_instr_agent.monitor [OBI_MEMORY_MON] RESET_STATE_IN_RESET
UVM_INFO @ 2.000 ns : uvma_obi_memory_mon.sv(178) uvm_test_top.env.obi_memory_data_agent.monitor [OBI_MEMORY_MON] RESET_STATE_IN_RESET
=E:[UpViolation] unique case violation at /home/e/core-v-verif/core-v-cores/cv32e40p/rtl/cv32e40p_load_store_unit.sv:419:5
  Time: 2.000 ns
  Instance: uvmt_cv32e40p_tb.dut_wrap.cv32e40p_tb_wrapper_i.cv32e40p_top_i.core_i
  No item hit.
UVM_INFO @ 9.400 ns : uvma_clknrst_drv.sv(164) uvm_test_top.env.clknrst_agent.driver [CLKNRST] De-asserting reset
UVM_INFO @ 9.400 ns : uvme_cv32e40p_reset_vseq.sv(83) uvm_test_top.env.vsequencer@@reset_vseq [RST_VSEQ] Done reset, waiting 7.400 ns for DUT to stabilize
UVM_INFO @ 9.400 ns : uvma_obi_memory_mon.sv(181) uvm_test_top.env.obi_memory_instr_agent.monitor [OBI_MEMORY_MON] RESET_STATE_POST_RESET
UVM_INFO @ 9.400 ns : uvma_obi_memory_mon.sv(181) uvm_test_top.env.obi_memory_data_agent.monitor [OBI_MEMORY_MON] RESET_STATE_POST_RESET
UVM_INFO @ 16.800 ns : uvme_cv32e40p_reset_vseq.sv(86) uvm_test_top.env.vsequencer@@reset_vseq [RST_VSEQ] Starting clock with period of 1.500 ns
UVM_INFO @ 16.800 ns : uvma_clknrst_if.sv(65) reporter [CLKNRST] Changing clock period to 1.500 ns
UVM_INFO @ 16.800 ns : uvmt_cv32e40p_base_test.sv(284) uvm_test_top [BASE TEST] Finished reset virtual sequence:
--------------------------------------------------------------------------------------------
Name                           Type                        Size  Value
--------------------------------------------------------------------------------------------
reset_vseq                     uvme_cv32e40p_reset_vseq_c  -     @710
  num_clk_before_reset         integral                    32    'd50
  rst_deassert_period          integral                    32    'd7400
  post_rst_wait                integral                    32    'd7400
  begin_time                   time                        64    0.000 ns
  end_time                     time                        64    17.000 ns
  depth                        int                         32    'd1
  parent sequence (name)       string                      0     ""
  parent sequence (full name)  string                      0     ""
  sequencer                    string                      27    uvm_test_top.env.vsequencer
  req                          object                      -     <null>
  rsp                          object                      -     <null>
--------------------------------------------------------------------------------------------

UVM_INFO @ 16.800 ns : uvmt_cv32e40p_base_test.sv(309) uvm_test_top [BASE TEST] set load_instr_mem
UVM_INFO @ 114.300 ns : uvmt_cv32e40p_firmware_test.sv(156) uvm_test_top [TEST] Started RUN
UVM_INFO @ 96543.300 ns : uvmt_cv32e40p_firmware_test.sv(165) uvm_test_top [TEST] Finished RUN: exit status is 1
UVM_INFO @ 96543.300 ns : uvm_objection.svh(1270) reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_ERROR @ 96543.300 ns : uvmt_cv32e40p_base_test.sv(352) uvm_test_top [END_OF_TEST] DUT WRAPPER virtual peripheral flagged test failure.
UVM_ERROR @ 96543.300 ns : uvmt_cv32e40p_base_test.sv(357) uvm_test_top [END_OF_TEST] DUT WRAPPER virtual peripheral signaled exit_value=1.
UVM_INFO @ 96543.300 ns : uvm_report_server.svh(847) reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

Quit count :     2 of    10
** Report counts by severity
UVM_INFO :   52
UVM_WARNING :    0
UVM_ERROR :    2
UVM_FATAL :    0
** Report counts by id
[BASE TEST]     6
[CFGDBGET]     1
[CLKNRST]     3
[CV32E40PCORECTRLAGT]     1
[CV32E40PVPSEQ]     1
[E40PVPSTATUS]     1
[END_OF_TEST]     2
[FETCHTOGGLE]     1
[MEMREADMEMH]     1
[OBIVPSEQ]    22
[OBI_MEMORY_MON]     4
[RNTST]     1
[RST_VSEQ]     3
[TEST]     3
[TEST_CFG]     1
[TEST_DONE]     1
[UVM/RELNOTES]     1
[UVME_CV32E40P_ENV]     1

=N:9 SVA assertion evaluations in progress at end of simulation, all considered passed.
=N:1 SVA cover evaluation in progress at end of simulation, 0 considered passed.
SVA Summary:  123 assertions, 3954123 evaluations, 986408 nonvacuous passes, 62 disables
SVA Summary:  194 cover property statements, 6241950 evaluations, 0 nonvacuous passes, 194 statements not covered

uvmt_cv32e40p_tb.end_of_test: *** Test Summary ***

    FFFFFFFF   AAAAAA   IIIIII  LL        EEEEEEEE  DDDDDDD
    FF        AA    AA    II    LL        EE        DD    DD
    FF        AA    AA    II    LL        EE        DD    DD
    FFFFF     AAAAAAAA    II    LL        EEEEE     DD    DD
    FF        AA    AA    II    LL        EE        DD    DD
    FF        AA    AA    II    LL        EE        DD    DD
    FF        AA    AA  IIIIII  LLLLLLLL  EEEEEEEE  DDDDDDD
    --------------------------------------------------------
                       SIMULATION FAILED
    --------------------------------------------------------
=N:[WriteMetrics] Writing coverage metrics...
=T:Simulation terminated by $finish at time 96543300 (/home/e/AltairDSim/2025.1/uvm/1.2/src/base/uvm_root.svh:517);
Run directory: /home/e/core-v-verif/cv32e40p/sim/uvmt/dsim_results/default/generic_exception_test/0
  System timescale is 1ps / 1ps
  Altair DSim version: 2025.1.0 (b:R #c:449 h:df8da7d488 os:rocky_8.10)
  Random seed: 261377808

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