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and event routing on a silicon wafer substrate. It enables fast emulation of
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complex neural dynamics and exploration of STDP-type synaptic plasticity.
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title: BrainScaleS-1 — Heidelberg University
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type: neuromorphic-hardware
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---
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The BrainScaleS-1 accelerated neuromorphic system is an wafer-scale integrated circuit architecture for emulating biologically-inspired spiking neural networks.
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It was developed by researchers at the Heidelberg University and collaborators.
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Key features of the BrainScaleS-1 system include:
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## System Architecture
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- 20 wafers comprising 384 ASICs interconnected by a configurable circuit-switched event routing network on a silicon wafer
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- Every ASIC integrate a custom analog core with 512 neuron circuits, 112k plastic synapses, floating-gate-based analog parameter storage, STDP-type long-term and STP-type short-term plasticity and an event routing network
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## Neural and Synapse Circuits
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- Implements the Adaptive Exponential Integrate-and-Fire (AdEx) neuron model with individually configurable model parameters
- BrainScaleS OS provides a full software stack including:
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- High-level PyNN-based experiment interfaces
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- C++ core libraries for configuration, calibration and control
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- Mapping and routing tools to translate neural models onto hardware
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- Allows both novice and expert usage with varying levels of abstraction
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- Supports batch-mode and hybrid-mode experiments (chip-in-the-loop)
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## Applications and Experiments
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- Accelerated (10,000-fold compared to biological real time) emulation of complex spiking neuron dynamics
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- Exploration of synaptic plasticity models and critical network dynamics at biological timescales
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The accelerated operation and flexible architecture facilitate applications in computational neuroscience research.
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## Related publications
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| Date | Title | Authors | Venue/Source |
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|------|-------|----------|------------- |
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| September 2023 |[From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system](https://doi.org/10.1088/2634-4386/acf7e4)| Hartmut Schmidt, José Montes, Andreas Grübl, Maurice Güttler, Dan Husmann, Joscha Ilmberger, Jakob Kaiser, Christian Mauch, Eric Müller, Lars Sterzenbach, Johannes Schemmel and Sebastian Schmitt | Neuromorphic Computing and Engineering |
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| May 2022 |[The operating system of the neuromorphic BrainScaleS-1 system](https://doi.org/10.1016/j.neucom.2022.05.081)| Eric Müller, Sebastian Schmitt, Christian Mauch, Sebastian Billaudelle, Andreas Grübl, Maurice Güttler, Dan Husmann, Joscha Ilmberger, Sebastian Jeltsch, Jakob Kaiser, Johann Klähn, Mitja Kleider, Christoph Koke, José Montes, Paul Müller, Johannes Partzsch, Felix Passenberg, Hartmut Schmidt, Bernhard Vogginger, Jonas Weidner, Christian Mayr, Johannes Schemmel | Neurocomputing |
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| March 2016 |[Neuromorphic Computer Coming Online](https://www.uni-heidelberg.de/presse/news2016/pm20160316-neuromorphic-computer-coming-online.html)| No author listed | Press Release by Heidelberg University |
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| June 2010 |[A wafer-scale neuromorphic hardware system for large-scale neural modeling](https://doi.org/10.1109/ISCAS.2010.5536970)| Johannes Schemmel, Daniel Brüderle, Andreas Grübl, Matthias Hock, Karlheinz Meier, Sebastian Millner | 2010 IEEE International Symposium on Circuits and Systems (ISCAS) |
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| June 2008 |[Wafer-scale integration of analog neural networks](https://doi.org/10.1109/IJCNN.2008.4633828)| Johannes Schemmel, Johannes Fieres, Karlheinz Meier | 2008 IEEE International Joint Conference on Neural Networks (IJCNN) |
and event routing. It enables fast emulation of complex neural dynamics and exploration
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of synaptic plasticity rules. The architecture supports training of deep spiking
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and non-spiking neural networks using hybrid techniques like surrogate gradients.
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title: BrainScaleS 2 - Universität Heidelberg
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title: BrainScaleS-2 — Heidelberg University
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type: neuromorphic-hardware
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---
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The BrainScaleS-2 accelerated neuromorphic system is an integrated circuit architecture for emulating biologically-inspired spiking neural networks. It was developed by researchers at the Heidelberg University and collaborators. Key features of the BrainScaleS-2 system include:
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## System Architecture
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- Single-chip ASIC integrating a custom analog core with 512 neuron circuits, 212k plastic synapses, analog parameter storage, embedded processors for digital control and plasticity, and an event routing network
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- Single-chip ASIC integrating a custom analog core with 512 neuron circuits, 131k plastic synapses, analog parameter storage, embedded processors for digital control and plasticity, and an event routing network
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- Processor cores run a software stack with a C++ compiler and support hybrid spiking and non-spiking neural network execution
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- Capable as a unit of scale for larger multi-chip or wafer-scale systems
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@@ -57,9 +57,9 @@ The BrainScaleS-2 accelerated neuromorphic system is an integrated circuit archi
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- Massively parallel readout of analog observables enables gradient-based and surrogate gradient optimization approaches
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## Applications and Experiments
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- Accelerated emulation of complex spiking neuron dynamics, multi-compartment models, and path integration circuits
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- Accelerated (1,000-fold compared to biological real time) emulation of complex spiking neural network dynamics, including configurable multi-compartmental cell morphologies
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- Exploration of synaptic plasticity models and critical network dynamics at biological timescales
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- Training of deep spiking neural networks using surrogate gradient techniques
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- Training of deep spiking neural networks using surrogate and exact gradient techniques
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- Non-spiking neural network execution leveraging synaptic crossbar for analog matrix multiplication
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The accelerated operation and flexible architecture facilitate applications in computational neuroscience research and novel machine learning approaches. The system design serves as a scalable basis for future large-scale neuromorphic computing platforms.
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| Date | Title | Authors | Venue/Source |
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|------|-------|----------|------------- |
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| January 2022 |[The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity](https://arxiv.org/abs/2201.11063)| Christian Pehle, Sebastian Billaudelle, Benjamin Cramer, Jakob Kaiser, Korbinian Schreiber, Yannik Stradmann, Johannes Weis, Aron Leibfried, Eric Müller, Johannes Schemmel | arXiv |
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| April 2024 |[jaxsnn: Event-driven gradient estimation for analog neuromorphic hardware](https://doi.org/10.1109/NICE61972.2024.10548709)| Eric Müller, Moritz Althaus, Elias Arnold, Philipp Spilger, Christian Pehle, Johannes Schemmel | 2024 Neuro-Inspired Computational Elements Conference (NICE) |
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| April 2023 |[hxtorch.snn: Machine-learning-inspired Spiking Neural Network Modeling on BrainScaleS-2](https://doi.org/10.1145/3584954.3584993)| Philipp Spilger, Elias Arnold, Luca Blessing, Christian Mauch, Christian Pehle, Eric Müller, Johannes Schemmel | 2023 Neuro-Inspired Computational Elements Conference (NICE) |
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| May 2022 |[A Scalable Approach to Modeling on Accelerated Neuromorphic Hardware](https://doi.org/10.3389/fnins.2022.884128)| Eric Müller, Elias Arnold, Oliver Breitwieser, Milena Czierlinski, Arne Emmel, Jakob Kaiser, Christian Mauch, Sebastian Schmitt, Philipp Spilger, Raphael Stock, Yannik Stradmann, Johannes Weis, Andreas Baumbach, Sebastian Billaudelle, Benjamin Cramer, Falk Ebert, Julian Göltz, Joscha Ilmberger, Vitali Karasenko, Mitja Kleider, Aron Leibfried, Christian Pehle, Johannes Schemmel | Frontiers in Neuroscience (Neuromorphic Engineering) |
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| February 2022 |[The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity](https://doi.org/10.3389/fnins.2022.795876)| Christian Pehle, Sebastian Billaudelle, Benjamin Cramer, Jakob Kaiser, Korbinian Schreiber, Yannik Stradmann, Johannes Weis, Aron Leibfried, Eric Müller, Johannes Schemmel | Frontiers in Neuroscience (Neuromorphic Engineering) |
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| January 2021 |[hxtorch: PyTorch for BrainScaleS-2 — Perceptrons on Analog Neuromorphic Hardware](https://doi.org/10.1007/978-3-030-66770-2_14)| Philipp Spilger, Eric Müller, Arne Emmel, Aron Leibfried, Christian Mauch, Christian Pehle, Johannes Weis, Oliver Breitwieser, Sebastian Billaudelle, Sebastian Schmitt, Timo C. Wunderlich, Yannik Stradmann, Johannes Schemmel | 2020 International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM) |
summary: The Spikey chip is an accelerated spiking neuromorphic system integrating
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384 integrate-and-fire neurons, 98k plastic synapses, and event routing.
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It enables fast emulation of complex neural dynamics and exploration of STDP-type synaptic plasticity.
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title: Spikey — Heidelberg University
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type: neuromorphic-hardware
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---
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The Spikey accelerated neuromorphic system is an integrated circuit architecture for emulating biologically-inspired spiking neural networks.
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It was developed by researchers at the Heidelberg University.
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Key features of the Spikey system include:
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## System Architecture
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- Single-chip ASIC integrating a custom analog core with 384 neuron circuits, 98k plastic synapses, analog parameter storage, and an event routing network
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- Synapses support STDP-type long-term and STP-type short-term plasticity.
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## Neural and Synapse Circuits
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- Implements the Leaky Integrate-and-Fire (LIF) neuron model with individually configurable model parameters
- Accelerated (50,000–100,000-fold compared to biological real time) emulation of complex spiking neuron dynamics
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- Exploration of synaptic plasticity models and critical network dynamics at biological timescales
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The accelerated operation and flexible architecture facilitate applications in computational neuroscience research.
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## Related publications
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| Date | Title | Authors | Venue/Source |
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|------|-------|----------|------------- |
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| February 2013 |[Six networks on a universal neuromorphic computing substrate](https://doi.org/10.3389/fnins.2013.00011)| Thomas Pfeil, Andreas Grübl, Sebastian Jeltsch, Eric Müller, Paul Müller, Mihai A. Petrovici, Michael Schmuker, Daniel Brüderle, Johannes Schemmel, Karlheinz Meier | Frontiers in Neuroscience (Neuromorphic Engineering) |
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| July 2012 |[Is a 4-bit synaptic weight resolution enough? – constraints on enabling spike-timing dependent plasticity in neuromorphic hardware](https://doi.org/10.3389/fnins.2012.00090)| Thomas Pfeil, Tobias C. Potjans, Sven Schrader, Wiebke Potjans, Johannes Schemmel, Markus Diesmann, Karlheinz Meier | Frontiers in Neuroscience (Neuromorphic Engineering) |
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| June 2009 |[Establishing a Novel Modeling Tool: a Python-based Interface for a Neuromorphic Hardware System](https://doi.org/10.3389/neuro.11.017.2009)| Daniel Brüderle, Eric Müller, Andrew Davison, Eilif Muller, Johannes Schemmel, Karlheinz Meier | Frontiers Neuroinformatics |
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| June 2007 |[Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons](https://doi.org/10.1109/ISCAS.2007.378289)| Johannes Schemmel, Daniel Bruderle, Karlheinz Meier, Boris Ostendorf | 2007 IEEE International Symposium on Circuits and Systems (ISCAS) |
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| July 2006 |[Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model](https://doi.org/10.1109/IJCNN.2006.246651)| Johannes Schemmel, Andreas Grübl, Karlheinz Meier, Eilif Mueller | 2006 IEEE International Joint Conference on Neural Network (IJCNN) |
**hxtorch** is a deep learning Python library used for numerical simulation, neuromorphic emulation and training of spiking neural networks (SNNs). Built on top of PyTorch, it integrates the automatic differentiation and modular design of the PyTorch ecosystem with neuromorphic experiment execution, enabling hardware-in-the-loop training workflows on the neuromorphic hardware system BrainScaleS-2 .
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The library abstracts the hardware configuration and experiment execution, while allowing users to define networks using familiar PyTorch modules such as LIF and LI neuron layers and synaptic connections. By separating network definition from execution, hxtorch supports both software simulation and hardware emulation within a single, unified API.
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The framework supports surrogate gradient-based learning, custom backward functions and seamless conversion between sparse, event-based observables and dense PyTorch tensors. It is designed to facilitate iterative model development, hybrid simulation/emulation and the integration of hardware observables such as spike trains and membrane voltages directly into the training loop.
**jaxsnn** is a deep learning Python library used for event-based numerical simulation, neuromorphic emulation and training of spiking neural networks (SNNs) with BrainScaleS-2 neuromorphic hardware in-the-loop. It is maintained by the Electronic Visions group at Heidelberg University.
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Unlike conventional deep learning libraries, which rely on dense tensor representations and time-discretized updates, jaxsnn is designed for event-driven computation. It directly operates on asynchronous spike events and supports gradient-based learning using methods such as EventProp and “Fast & Deep” spike-time coding. The library leverages JAX’s automatic differentiation, just-in-time compilation (via XLA) and support for hardware acceleration to enable efficient and composable training of biologically inspired SNNs.
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jaxsnn is tailored for integration with analog neuromorphic systems such as BrainScaleS-2. It supports hardware-in-the-loop training by offloading the forward pass to neuromorphic hardware while computing gradients in software. For development and testing, jaxsnn can also be used as a pure simulator framework.
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With native event-based processing, support for custom VJP definitions and a modular, JAX-compatible design, jaxsnn provides a flexible platform for bridging the gap between modern machine learning tools and the sparse, real-time nature of neuromorphic computing. It is particularly suited for research on energy-efficient learning algorithms, continuous-time dynamics, and hardware-constrained SNN modeling.
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