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content/english/neuromorphic-computing/hardware/akida-brainchip/index.md

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twitter: https://twitter.com/BrainChip_inc
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wikipedia: https://en.wikipedia.org/wiki/BrainChip
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product:
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announced_date: 2023-01-01
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announced_date: 2022-10-01
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applications: Smart sensing, one-shot learning
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chip_type: Digital
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synapses: Configurable
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neurons: 256, Configurable
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synapses: Configurable, 8MB SRAM
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neurons: Configurable
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weight_bits: 1,2,4,8
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activation_bits: 1,2,4,8
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on_chip_learning: true
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power: ~30 mW
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release_year: 2023
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release_date: 2023-10-01
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release_year: 2022
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release_date: 2022-10-01
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software: MetaTF
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status:
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announced: true
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released: true
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retired: false
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synapse hardware: 8-Mb SRAM.
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product_name: Akida
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summary: BrainChip's Akida is an ultra-low-power neuromorphic processor inspired by
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the brain's neural architecture. It accelerates complex AI at the edge through event-based

content/english/neuromorphic-computing/hardware/brainscales-2-universitat-heidelberg/index.md

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status:
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announced: true
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released: true
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retired: true
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retired: false
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product_name: BrainScaleS 2
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summary: The BrainScaleS-2 is an accelerated spiking neuromorphic system-on-chip integrating
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512 adaptive integrate-and-fire neurons, 212k plastic synapses, embedded processors,

content/english/neuromorphic-computing/hardware/tianjic-tsinghua-university/index.md

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twitter: null
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wikipedia: https://en.wikipedia.org/wiki/Tsinghua_University
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product:
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announced_date: 2015-08-01
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announced_date: 2019-08-01
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applications: ANN/SNN acceleration
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chip_type: Digital
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neurons: 40k
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activation_bits: null
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on_chip_learning: false
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power: ~1 W
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release_date: 2015-08-01
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release_year: 2015
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release_date: 2020-02-13
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release_year: 2020
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software: Custom
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status:
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announced: true
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## Related publications
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| Date | Title | Authors | Venue/Source |
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|------|-------|----------|------------- |
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| August 2015 | [Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation](https://ieeexplore.ieee.org/document/8998338) | Lei Deng; Guanrui Wang; Guoqi Li; Shuangchen Li; Ling Liang; Maohua Zhu; Yujie Wu; Zheyu Yang; Zhe Zou; Jing Pei; Zhenzhi Wu; Xing Hu; Yufei Ding; Wei He; Yuan Xie; Luping Shi | IEEE Journal of Solid-State Circuits |
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| February 2020 | [Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation](https://ieeexplore.ieee.org/document/8998338) | Lei Deng; Guanrui Wang; Guoqi Li; Shuangchen Li; Ling Liang; Maohua Zhu; Yujie Wu; Zheyu Yang; Zhe Zou; Jing Pei; Zhenzhi Wu; Xing Hu; Yufei Ding; Wei He; Yuan Xie; Luping Shi | IEEE Journal of Solid-State Circuits |

content/english/neuromorphic-computing/hardware/xylo-synsense/index.md

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announced_date: 2022
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applications: Smart sensing
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chip_type: Digital
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neurons: null
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neurons: 1000
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synapses: 278000
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weight_bits: null
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activation_bits: null
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weight_bits: 8
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activation_bits: 8
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on_chip_learning: false
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power: ~5 mW
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release_year: 2022
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product_name: Xylo
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summary: Xylo is a 28nm 1000 neuron digital spiking neural network inference chip
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optimized for ultra low power edge deployment of trained SNNs, with flexible architecture
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optimized for ultra-low power edge deployment of trained SNNs, with a flexible architecture
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to map various network topologies.
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title: Xylo - SynSense
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---
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Xylo is a series of ultra-low-power devices for sensory inference, featuring a digital SNN core adaptable to various sensory inputs like audio and bio-signals. Its SNN core uses an integer-logic CuBa-LIF neuron model with customizable parameters for each synapse and neuron, supporting a wide range of network architectures. The Xylo Audio 2 model (SYNS61201) specifically includes 8-bit synaptic weights, 16-bit synaptic and membrane states, two synaptic states per neuron, 16 input channels, 1000 hidden neurons, 8 output neurons with 8 output channels, a maximum fan-in of 63, and a total of 64,000 synaptic weights.
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For more detailed technical information, see https://rockpool.ai/devices/xylo-overview.html.
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The Rockpool toolchain contains quantizaton methods designed for Xylo, as well as bit-accurate simulations of Xylo devices.
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The Rockpool toolchain contains quantization methods designed for Xylo and bit-accurate simulations of Xylo devices.
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## Overview
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Xylo is an application-specific integrated circuit (ASIC) chip optimized specifically for SNN inference. Key features include:
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- All-digital design using integer arithmetic for efficient simulation of LIF neuron dynamics
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- Supports up to 1000 LIF neurons with configurable synaptic and membrane time constants, thresholds and biases for each neuron
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- Supports up to 1000 LIF neurons with configurable synaptic and membrane time constants, thresholds, and biases for each neuron
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- 16 input channels and 8 output channels using asynchronous spiking events
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- Flexible network architecture including support for recurrent connectivity to map deep networks
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- Ultra low power consumption, with 219 μW idle power and 93 μW dynamic inference power measured on audio classification application
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- Ultra-low power consumption, with 219 μW idle power and 93 μW dynamic inference power measured on audio classification application
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The chip is fabricated in a 28nm CMOS process and occupies 6.5 mm2 die area. It can operate at clock frequencies up to 250 MHz.
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The chip is fabricated in a 28nm CMOS process and occupies a 6.5 mm2 die area. It can operate at clock frequencies up to 250 MHz.
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## Architecture
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## Software Tools
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Xylo leverages the Rockpool ecosystem for mapping and deploying SNNs. The Rockpool library and Python API abstract the SNN programming to high levels, enabling machine learning engineers to easily train networks using standard methods like backpropagation. A compiler handles mapping optimized networks onto the Xylo substrate.
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Xylo leverages the Rockpool ecosystem for mapping and deploying SNNs. The Rockpool library and Python API abstract the SNN programming to high levels, enabling machine learning engineers to train networks easily using standard methods like backpropagation. A compiler handles mapping optimized networks onto the Xylo substrate.
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## Applications
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The flexibility to implement generic deep network topologies makes Xylo suitable for a variety of edge deployments in domains such as audio, time series, and control. Example applications demonstrated include low power keyword spotting, biosignal classification, and robotic control. Ultra low idle and dynamic power consumption enables continuous background processing in power constrained environments.
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The flexibility to implement generic deep network topologies makes Xylo suitable for a variety of edge deployments across domains such as audio, time series, and control. Example applications demonstrated include low-power keyword spotting, biosignal classification, and robotic control. Ultra-low idle and dynamic power consumption enables continuous background processing in power-constrained environments.
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## Related publications
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| Date | Title | Authors | Venue/Source |

content/english/workshops/visual-place-recognition-tobias-fischer/index.md

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title: "Advances in Neuromorphic Visual Place Recognition"
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author:
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- Tobias Fischer
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date: 2024-03-28
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start_time: 11:00
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date: 2024-04-18
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start_time: 23:00
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description: "Tobias Fischer shares advances in neuromorphic visual place recognition."
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end_time: 12:30
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end_time: 00:30
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time_zone: CET
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draft: false
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upcoming: false
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image: advances-in-neuromorphic-visual-place-rec.png
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speaker_photo: speaker.jpeg
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speaker_bio: "Tobias conducts interdisciplinary research at the intersection of intelligent robotics, computer vision, and computational cognition. My main goal is to develop high-performing, bio-inspired computer vision algorithms that simultaneously examine animals/humans and robots' perceptional capabilities. He is a Lecturer (Assistant Professor) in Queensland University of Technology's Centre for Robotics. He joined the Centre as an Associate Investigator and Research Fellow in January 2020. Previously, he was a postdoctoral researcher in the Personal Robotics Lab at Imperial College London. He received a PhD from Imperial College in January 2019. His thesis was awarded the UK Best Thesis in Robotics Award 2018 and the Eryl Cadwaladr Davies Award for the best thesis in Imperial's EEE Department in 2017-2018. He previously received an M.Sc. degree (distinction) in Artificial Intelligence from The University of Edinburgh in 2014 and a B.Sc. degree in Computer Engineering from Ilmenau University of Technology, Germany, in 2013. His works have attracted two best poster awards, one best paper award, and he was the senior author of the winning submission to the Facebook Mapillary Place Recognition Challenge 2020."
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speaker_bio: "Tobias conducts interdisciplinary research at the intersection of intelligent robotics, computer vision, and computational cognition. My main goal is to develop high-performing, bio-inspired computer vision algorithms that simultaneously examine animals/humans and robots' perceptional capabilities. He is a Senior Lecturer (US: Associate Professor) and Chief Investigator in Queensland University of Technology's Centre for Robotics. He is also a recipient of the prestigious Discovery Early Career Researcher Award (DECRA) by the Australian Research Council. He joined the Centre as an Associate Investigator and Research Fellow in January 2020. Previously, he was a postdoctoral researcher in the Personal Robotics Lab at Imperial College London. He received a PhD from Imperial College in January 2019. His thesis was awarded the UK Best Thesis in Robotics Award 2018 and the Eryl Cadwaladr Davies Award for the best thesis in Imperial's EEE Department in 2017-2018. He previously received an M.Sc. degree (distinction) in Artificial Intelligence from The University of Edinburgh in 2014 and a B.Sc. degree in Computer Engineering from Ilmenau University of Technology, Germany, in 2013. His works have attracted two best poster awards, one best paper award, and he was the senior author of the winning submission to the Facebook Mapillary Place Recognition Challenge 2020."
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themes/hugoplate/layouts/partials/hardware/product-info.html

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<h2 class="text-2xl font-bold mb-4 col-span-3">{{ $product }} At A Glance</h2>
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{{ with .announced_date }}<div><strong>Announced Date:</strong> {{ . }}</div>{{ end }}
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