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* reserved.
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* Copyright (c) 2020 Research Organization for Information Science
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* and Technology (RIST). All rights reserved.
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+ * Copyright (c) 2021 Cisco Systems, Inc. All rights reserved.
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* $COPYRIGHT$
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*
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* Additional copyrights may follow
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#include "ompi_config.h"
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#include "opal/util/printf.h"
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+ #include "ompi/include/mpi_portable_platform.h"
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#include "ompi/constants.h"
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#include "ompi/op/op.h"
@@ -35,6 +37,18 @@ static struct ompi_op_base_module_1_0_0_t *
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avx_component_op_query (struct ompi_op_t * op , int * priority );
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static int avx_component_register (void );
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+ static mca_base_var_enum_value_flag_t avx_support_flags [] = {
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+ { .flag = 0x001 , .string = "SSE" },
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+ { .flag = 0x002 , .string = "SSE2" },
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+ { .flag = 0x004 , .string = "SSE3" },
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+ { .flag = 0x008 , .string = "SSE4.1" },
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+ { .flag = 0x010 , .string = "AVX" },
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+ { .flag = 0x020 , .string = "AVX2" },
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+ { .flag = 0x100 , .string = "AVX512F" },
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+ { .flag = 0x200 , .string = "AVX512BW" },
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+ { .flag = 0 , .string = NULL },
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+ };
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+
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/**
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* A slightly modified code from
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* https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family
@@ -177,15 +191,38 @@ static int avx_component_close(void)
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static int
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avx_component_register (void )
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{
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- int32_t requested_flags = mca_op_avx_component .flags = has_intel_AVX_features ();
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+ mca_op_avx_component .supported =
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+ mca_op_avx_component .flags = has_intel_AVX_features ();
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+
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+ // MCA var enum flag for conveniently seeing SSE/MMX/AVX support
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+ // values
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+ mca_base_var_enum_flag_t * new_enum_flag ;
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+ (void ) mca_base_var_enum_create_flag ("op_avx_support_flags" ,
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+ avx_support_flags , & new_enum_flag );
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+ (void ) mca_base_var_enum_register ("ompi" , "op" , "avx" , "support_flags" ,
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+ & new_enum_flag );
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+
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+ (void ) mca_base_component_var_register (& mca_op_avx_component .super .opc_version ,
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+ "capabilities" ,
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+ "Level of SSE/MMX/AVX support available in the current environment" ,
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+ MCA_BASE_VAR_TYPE_INT ,
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+ & (new_enum_flag -> super ), 0 , 0 ,
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+ OPAL_INFO_LVL_4 ,
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+ MCA_BASE_VAR_SCOPE_CONSTANT ,
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+ & mca_op_avx_component .supported );
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+
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(void ) mca_base_component_var_register (& mca_op_avx_component .super .opc_version ,
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"support" ,
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- "Level of SSE/MMX/AVX support to be used (combination of processor capabilities as follow SSE 0x01, SSE2 0x02, SSE3 0x04, SSE4.1 0x08, AVX 0x010, AVX2 0x020, AVX512F 0x100, AVX512BW 0x200) capped by the local architecture capabilities" ,
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- MCA_BASE_VAR_TYPE_INT , NULL , 0 , 0 ,
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- OPAL_INFO_LVL_6 ,
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+ "Level of SSE/MMX/AVX support to be used, capped by the local architecture capabilities" ,
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+ MCA_BASE_VAR_TYPE_INT ,
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+ & (new_enum_flag -> super ), 0 , 0 ,
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+ OPAL_INFO_LVL_4 ,
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MCA_BASE_VAR_SCOPE_LOCAL ,
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& mca_op_avx_component .flags );
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- mca_op_avx_component .flags &= requested_flags ;
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+ OBJ_RELEASE (new_enum_flag );
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+
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+ mca_op_avx_component .flags &= mca_op_avx_component .supported ;
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+
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return OMPI_SUCCESS ;
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}
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