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238 | 238 | #define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)
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239 | 239 | #define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
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240 | 240 |
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| 241 | +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002 |
| 242 | +#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8) |
| 243 | + |
241 | 244 | #define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\
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242 | 245 | LAN887X_INT_MSK_LINK_DOWN_MSK)
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243 | 246 |
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@@ -1286,6 +1289,15 @@ static int lan887x_phy_init(struct phy_device *phydev)
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1286 | 1289 | if (IS_ERR(priv->clock))
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1287 | 1290 | return PTR_ERR(priv->clock);
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1288 | 1291 |
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| 1292 | + /* Enable pin mux for EVT */ |
| 1293 | + phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 1294 | + LAN887X_MX_CHIP_TOP_REG_CONTROL1, |
| 1295 | + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN, |
| 1296 | + LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN); |
| 1297 | + |
| 1298 | + /* Initialize pin numbers specific to PEROUT */ |
| 1299 | + priv->clock->event_pin = 3; |
| 1300 | + |
1289 | 1301 | priv->init_done = true;
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1290 | 1302 | }
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1291 | 1303 |
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@@ -2154,7 +2166,7 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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2154 | 2166 |
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2155 | 2167 | module_phy_driver(microchip_t1_phy_driver);
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2156 | 2168 |
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2157 |
| -static const struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { |
| 2169 | +static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = { |
2158 | 2170 | { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
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2159 | 2171 | { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
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2160 | 2172 | { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
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