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Merge tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pulll more Renesas clk driver updates from Geert Uytterhoeven: - Add support for the RZ/G3S (R9A08G045) SoC - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rcar-gen3: Extend SDnH divider table dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
2 parents 2952134 + 4bce4be commit c3f1874

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-85
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‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ properties:
2727
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
2828
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
2929
- renesas,r9a07g054-cpg # RZ/V2L
30+
- renesas,r9a08g045-cpg # RZ/G3S
3031
- renesas,r9a09g011-cpg # RZ/V2M
3132

3233
reg:

‎drivers/clk/renesas/Kconfig

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ config CLK_RENESAS
3737
select CLK_R9A07G043 if ARCH_R9A07G043
3838
select CLK_R9A07G044 if ARCH_R9A07G044
3939
select CLK_R9A07G054 if ARCH_R9A07G054
40+
select CLK_R9A08G045 if ARCH_R9A08G045
4041
select CLK_R9A09G011 if ARCH_R9A09G011
4142
select CLK_SH73A0 if ARCH_SH73A0
4243

@@ -179,6 +180,10 @@ config CLK_R9A07G054
179180
bool "RZ/V2L clock support" if COMPILE_TEST
180181
select CLK_RZG2L
181182

183+
config CLK_R9A08G045
184+
bool "RZ/G3S clock support" if COMPILE_TEST
185+
select CLK_RZG2L
186+
182187
config CLK_R9A09G011
183188
bool "RZ/V2M clock support" if COMPILE_TEST
184189
select CLK_RZG2L
@@ -215,7 +220,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
215220
This is a driver for R-Car USB2 clock selector
216221

217222
config CLK_RZG2L
218-
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
223+
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
219224
select RESET_CONTROLLER
220225

221226
# Generic

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3434
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3535
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3636
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
37+
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
3738
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
3839
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
3940

‎drivers/clk/renesas/r9a07g043-cpg.c

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,17 @@
1414

1515
#include "rzg2l-cpg.h"
1616

17+
/* Specific registers. */
18+
#define CPG_PL2SDHI_DSEL (0x218)
19+
20+
/* Clock select configuration. */
21+
#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
22+
#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)
23+
24+
/* Clock status configuration. */
25+
#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)
26+
#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)
27+
1728
enum clk_ids {
1829
/* Core Clock Outputs exported to DT */
1930
LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
@@ -78,6 +89,8 @@ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
7889
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
7990
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
8091

92+
static const u32 mtable_sdhi[] = { 1, 2, 3 };
93+
8194
static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
8295
/* External Clock Inputs */
8396
DEF_INPUT("extal", CLK_EXTAL),
@@ -123,8 +136,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
123136
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
124137
DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
125138
DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
126-
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),
127-
DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi),
139+
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
140+
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
141+
DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
142+
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
128143
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
129144
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
130145
};

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,17 @@
1515

1616
#include "rzg2l-cpg.h"
1717

18+
/* Specific registers. */
19+
#define CPG_PL2SDHI_DSEL (0x218)
20+
21+
/* Clock select configuration. */
22+
#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
23+
#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)
24+
25+
/* Clock status configuration. */
26+
#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)
27+
#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)
28+
1829
enum clk_ids {
1930
/* Core Clock Outputs exported to DT */
2031
LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
@@ -98,6 +109,8 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
98109
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
99110
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
100111

112+
static const u32 mtable_sdhi[] = { 1, 2, 3 };
113+
101114
static const struct {
102115
struct cpg_core_clk common[56];
103116
#ifdef CONFIG_CLK_R9A07G054
@@ -163,8 +176,10 @@ static const struct {
163176
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
164177
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
165178
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
166-
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
167-
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
179+
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
180+
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
181+
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
182+
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
168183
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
169184
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
170185
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 248 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,248 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* RZ/G3S CPG driver
4+
*
5+
* Copyright (C) 2023 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/r9a08g045-cpg.h>
14+
15+
#include "rzg2l-cpg.h"
16+
17+
/* RZ/G3S Specific registers. */
18+
#define G3S_CPG_PL2_DDIV (0x204)
19+
#define G3S_CPG_SDHI_DDIV (0x218)
20+
#define G3S_CPG_PLL_DSEL (0x240)
21+
#define G3S_CPG_SDHI_DSEL (0x244)
22+
#define G3S_CLKDIVSTATUS (0x280)
23+
#define G3S_CLKSELSTATUS (0x284)
24+
25+
/* RZ/G3S Specific division configuration. */
26+
#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3)
27+
#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
28+
#define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1)
29+
#define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1)
30+
31+
/* RZ/G3S Clock status configuration. */
32+
#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
33+
#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1)
34+
#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1)
35+
#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1)
36+
#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1)
37+
#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1)
38+
#define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1)
39+
#define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1)
40+
41+
#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1)
42+
#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1)
43+
#define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1)
44+
#define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1)
45+
46+
/* RZ/G3S Specific clocks select. */
47+
#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1)
48+
#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
49+
#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)
50+
#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
51+
52+
/* PLL 1/4/6 configuration registers macro. */
53+
#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
54+
55+
#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
56+
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
57+
.parent_names = (_parent_names), \
58+
.num_parents = ARRAY_SIZE((_parent_names)), \
59+
.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
60+
.flag = (_clk_flags))
61+
62+
enum clk_ids {
63+
/* Core Clock Outputs exported to DT */
64+
LAST_DT_CORE_CLK = R9A08G045_SWD,
65+
66+
/* External Input Clocks */
67+
CLK_EXTAL,
68+
69+
/* Internal Core Clocks */
70+
CLK_OSC_DIV1000,
71+
CLK_PLL1,
72+
CLK_PLL2,
73+
CLK_PLL2_DIV2,
74+
CLK_PLL2_DIV2_8,
75+
CLK_PLL2_DIV6,
76+
CLK_PLL3,
77+
CLK_PLL3_DIV2,
78+
CLK_PLL3_DIV2_4,
79+
CLK_PLL3_DIV2_8,
80+
CLK_PLL3_DIV6,
81+
CLK_PLL4,
82+
CLK_PLL6,
83+
CLK_PLL6_DIV2,
84+
CLK_SEL_SDHI0,
85+
CLK_SEL_SDHI1,
86+
CLK_SEL_SDHI2,
87+
CLK_SEL_PLL4,
88+
CLK_P1_DIV2,
89+
CLK_P3_DIV2,
90+
CLK_SD0_DIV4,
91+
CLK_SD1_DIV4,
92+
CLK_SD2_DIV4,
93+
94+
/* Module Clocks */
95+
MOD_CLK_BASE,
96+
};
97+
98+
/* Divider tables */
99+
static const struct clk_div_table dtable_1_2[] = {
100+
{ 0, 1 },
101+
{ 1, 2 },
102+
{ 0, 0 },
103+
};
104+
105+
static const struct clk_div_table dtable_1_8[] = {
106+
{ 0, 1 },
107+
{ 1, 2 },
108+
{ 2, 4 },
109+
{ 3, 8 },
110+
{ 0, 0 },
111+
};
112+
113+
static const struct clk_div_table dtable_1_32[] = {
114+
{ 0, 1 },
115+
{ 1, 2 },
116+
{ 2, 4 },
117+
{ 3, 8 },
118+
{ 4, 32 },
119+
{ 0, 0 },
120+
};
121+
122+
/* Mux clock names tables. */
123+
static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" };
124+
static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" };
125+
126+
/* Mux clock indices tables. */
127+
static const u32 mtable_sd[] = { 0, 2, 3 };
128+
static const u32 mtable_pll4[] = { 0, 1 };
129+
130+
static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
131+
/* External Clock Inputs */
132+
DEF_INPUT("extal", CLK_EXTAL),
133+
134+
/* Internal Core Clocks */
135+
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
136+
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
137+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
138+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
139+
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
140+
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
141+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
142+
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
143+
DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
144+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
145+
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
146+
DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8),
147+
DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6),
148+
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2),
149+
DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi,
150+
mtable_sd, 0, NULL),
151+
DEF_SD_MUX(".sel_sd1", CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi,
152+
mtable_sd, 0, NULL),
153+
DEF_SD_MUX(".sel_sd2", CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi,
154+
mtable_sd, 0, NULL),
155+
DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4,
156+
mtable_pll4, CLK_SET_PARENT_GATE, NULL),
157+
158+
/* Core output clk */
159+
DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
160+
0, 0, 0, NULL),
161+
DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS,
162+
dtable_1_32, 0, 0, 0, NULL),
163+
DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS,
164+
dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
165+
rzg3s_cpg_div_clk_notifier),
166+
DEF_G3S_DIV("SD1", R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS,
167+
dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
168+
rzg3s_cpg_div_clk_notifier),
169+
DEF_G3S_DIV("SD2", R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS,
170+
dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
171+
rzg3s_cpg_div_clk_notifier),
172+
DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4),
173+
DEF_FIXED(".sd1_div4", CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4),
174+
DEF_FIXED(".sd2_div4", CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4),
175+
DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
176+
DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS,
177+
dtable_1_32, 0, 0, 0, NULL),
178+
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2),
179+
DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS,
180+
dtable_1_32, 0, 0, 0, NULL),
181+
DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
182+
dtable_1_32, 0, 0, 0, NULL),
183+
DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
184+
DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
185+
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
186+
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
187+
};
188+
189+
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
190+
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
191+
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
192+
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
193+
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
194+
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
195+
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
196+
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
197+
DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4),
198+
DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5),
199+
DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6),
200+
DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7),
201+
DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8),
202+
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
203+
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
204+
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
205+
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
206+
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
207+
};
208+
209+
static const struct rzg2l_reset r9a08g045_resets[] = {
210+
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
211+
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
212+
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
213+
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
214+
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
215+
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
216+
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
217+
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
218+
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
219+
};
220+
221+
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
222+
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
223+
MOD_CLK_BASE + R9A08G045_IA55_CLK,
224+
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
225+
};
226+
227+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
228+
/* Core Clocks */
229+
.core_clks = r9a08g045_core_clks,
230+
.num_core_clks = ARRAY_SIZE(r9a08g045_core_clks),
231+
.last_dt_core_clk = LAST_DT_CORE_CLK,
232+
.num_total_core_clks = MOD_CLK_BASE,
233+
234+
/* Critical Module Clocks */
235+
.crit_mod_clks = r9a08g045_crit_mod_clks,
236+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks),
237+
238+
/* Module Clocks */
239+
.mod_clks = r9a08g045_mod_clks,
240+
.num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
241+
.num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
242+
243+
/* Resets */
244+
.resets = r9a08g045_resets,
245+
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
246+
247+
.has_clk_mon_regs = true,
248+
};

‎drivers/clk/renesas/rcar-cpg-lib.c

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,21 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
7070
#define STPnHCK BIT(9 - SDnSRCFC_SHIFT)
7171

7272
static const struct clk_div_table cpg_sdh_div_table[] = {
73+
/*
74+
* These values are recommended by the datasheet. Because they come
75+
* first, Linux will only use these.
76+
*/
7377
{ 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 },
74-
{ STPnHCK | 4, 16 }, { 0, 0 },
78+
{ STPnHCK | 4, 16 },
79+
/*
80+
* These values are not recommended because STPnHCK is wrong. But they
81+
* have been seen because of broken firmware. So, we support reading
82+
* them but Linux will sanitize them when initializing through
83+
* recalc_rate.
84+
*/
85+
{ STPnHCK | 0, 1 }, { STPnHCK | 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 },
86+
/* Sentinel */
87+
{ 0, 0 }
7588
};
7689

7790
struct clk * __init cpg_sdh_clk_register(const char *name,

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