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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A semi-large pile of clk driver fixes this time around. Nothing is touching the core so these fixes are fairly well contained to specific devices that use these clk drivers. - Some Allwinner SoC fixes to gracefully handle errors and mark an RTC clk as critical so that the RTC keeps ticking. - Fix AXI bus clks and RTC clk design for Microchip PolarFire SoC driver introduced this cycle. This has some devicetree bits acked by riscv maintainers. We're fixing it now so that the prior bindings aren't released in a major kernel version. - Remove a reset on Microchip PolarFire SoCs that broke when enabling CONFIG_PM. - Set a min/max for the Qualcomm graphics clk. This got broken by the clk rate range patches introduced this cycle" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource() clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as critical riscv: dts: microchip: reparent mpfs clocks clk: microchip: mpfs: add RTCREF clock control clk: microchip: mpfs: re-parent the configurable clocks dt-bindings: rtc: add refclk to mpfs-rtc dt-bindings: clk: mpfs: add defines for two new clocks dt-bindings: clk: mpfs document msspll dri registers riscv: dts: microchip: fix usage of fic clocks on mpfs clk: microchip: mpfs: mark CLK_ATHENA as critical clk: microchip: mpfs: fix parents for FIC clocks clk: qcom: clk-rcg2: fix gfx3d frequency calculation clk: microchip: mpfs: don't reset disabled peripherals clk: sunxi-ng: fix not NULL terminated coccicheck error
2 parents bd3d3ad + a91b05f commit c0e6265

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10 files changed

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Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,16 @@ properties:
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const: microchip,mpfs-clkcfg
2323

2424
reg:
25-
maxItems: 1
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items:
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- description: |
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clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
29+
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
30+
for the peripheral clocks.
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- description: |
32+
mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
@@ -51,7 +60,7 @@ examples:
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#size-cells = <2>;
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clkcfg: clock-controller@20002000 {
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compatible = "microchip,mpfs-clkcfg";
54-
reg = <0x0 0x20002000 0x0 0x1000>;
63+
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,19 @@ properties:
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to that of the RTC's count register.
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clocks:
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maxItems: 1
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items:
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- description: |
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AHB clock
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- description: |
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Reference clock: divided by the prescaler to create a time-based
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strobe (typically 1 Hz) for the calendar counter. By default, the rtc
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on the PolarFire SoC shares it's reference with MTIMER so this will
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be a 1 MHz clock.
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clock-names:
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items:
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- const: rtc
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- const: rtcref
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required:
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- compatible
@@ -48,11 +56,12 @@ additionalProperties: false
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examples:
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- |
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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rtc@20124000 {
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compatible = "microchip,mpfs-rtc";
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reg = <0x20124000 0x1000>;
54-
clocks = <&clkcfg 21>;
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clock-names = "rtc";
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clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
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clock-names = "rtc", "rtcref";
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interrupts = <80>, <81>;
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};
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...

arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
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reg = <0x0 0x41000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <2>;
10-
clocks = <&clkcfg CLK_FIC3>;
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clocks = <&fabric_clk3>;
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status = "disabled";
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};
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@@ -16,10 +16,22 @@
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reg = <0x0 0x44000000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkcfg CLK_FIC3>;
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clocks = <&fabric_clk3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <62500000>;
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};
31+
32+
fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@
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};
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&refclk {
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clock-frequency = <600000000>;
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clock-frequency = <125000000>;
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};
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&mmuart1 {

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@
141141
};
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};
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144-
refclk: msspllclk {
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refclk: mssrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
@@ -190,7 +190,7 @@
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191191
clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&refclk>;
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#clock-cells = <1>;
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};
@@ -393,8 +393,8 @@
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reg = <0x0 0x20124000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <80>, <81>;
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clocks = <&clkcfg CLK_RTC>;
397-
clock-names = "rtc";
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clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
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clock-names = "rtc", "rtcref";
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status = "disabled";
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};
400400

@@ -424,7 +424,7 @@
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<0 0 0 3 &pcie_intc 2>,
425425
<0 0 0 4 &pcie_intc 3>;
426426
interrupt-map-mask = <0 0 0 7>;
427-
clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
427+
clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic1", "fic3";
429429
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
430430
msi-parent = <&pcie>;

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