We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 9c85158 commit c0516ebCopy full SHA for c0516eb
drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -192,7 +192,16 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
192
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
193
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
194
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
195
+ DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
196
+ DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
197
+ DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
198
+ DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
199
+ DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
200
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
201
+ DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
202
+ DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
203
+ DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
204
+ DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
205
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
206
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
207
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
0 commit comments