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Zelong Dongsuperna9999
Zelong Dong
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superna9999
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arm64: dts: amlogic: Add Amlogic T7 reset controller
Add the device node and related header file for Amlogic T7 reset controller. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240422-t7-reset-v2-3-cb82271d3296@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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‎arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DTS_AMLOGIC_T7_RESET_H
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#define __DTS_AMLOGIC_T7_RESET_H
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/* RESET0 */
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/* 0-3 */
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#define RESET_USB 4
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#define RESET_U2DRD 5
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#define RESET_U3DRD 6
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#define RESET_U3DRD_PIPE0 7
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#define RESET_U2PHY20 8
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#define RESET_U2PHY21 9
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#define RESET_GDC 10
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#define RESET_HDMI20_AES 11
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#define RESET_HDMIRX 12
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#define RESET_HDMIRX_APB 13
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#define RESET_DEWARP 14
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/* 15 */
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#define RESET_HDMITX_CAPB3 16
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#define RESET_BRG_VCBUG_DEC 17
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#define RESET_VCBUS 18
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#define RESET_VID_PLL_DIV 19
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#define RESET_VDI6 20
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#define RESET_GE2D 21
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#define RESET_HDMITXPHY 22
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#define RESET_VID_LOCK 23
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#define RESET_VENC0 24
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#define RESET_VDAC 25
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#define RESET_VENC2 26
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#define RESET_VENC1 27
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#define RESET_RDMA 28
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#define RESET_HDMITX 29
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_MALI_CAPB3 33
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#define RESET_MALI 34
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#define RESET_DDR_APB 35
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#define RESET_DDR 36
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#define RESET_DOS_CAPB3 37
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#define RESET_DOS 38
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#define RESET_COMBO_DPHY_CHAN2 39
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#define RESET_DEBUG_B 40
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#define RESET_DEBUG_A 41
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#define RESET_DSP_B 42
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#define RESET_DSP_A 43
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#define RESET_PCIE_A 44
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#define RESET_PCIE_PHY 45
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#define RESET_PCIE_APB 46
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#define RESET_ANAKIN 47
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#define RESET_ETH 48
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#define RESET_EDP0_CTRL 49
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#define RESET_EDP1_CTRL 50
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#define RESET_COMBO_DPHY_CHAN0 51
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#define RESET_COMBO_DPHY_CHAN1 52
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#define RESET_DSI_LVDS_EDP_TOP 53
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#define RESET_PCIE1_PHY 54
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#define RESET_PCIE1_APB 55
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#define RESET_DDR_1 56
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/* 57 */
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#define RESET_EDP1_PIPELINE 58
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#define RESET_EDP0_PIPELINE 59
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#define RESET_MIPI_DSI1_PHY 60
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#define RESET_MIPI_DSI0_PHY 61
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#define RESET_MIPI_DSI_A_HOST 62
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#define RESET_MIPI_DSI_B_HOST 63
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/* RESET2 */
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#define RESET_DEVICE_MMC_ARB 64
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#define RESET_IR_CTRL 65
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#define RESET_TS_A73 66
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#define RESET_TS_A53 67
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#define RESET_SPICC_2 68
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#define RESET_SPICC_3 69
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#define RESET_SPICC_4 70
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#define RESET_SPICC_5 71
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#define RESET_SMART_CARD 72
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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#define RESET_RSA 75
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/* 76-79 */
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#define RESET_MSR_CLK 80
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#define RESET_SPIFC 81
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#define RESET_SAR_ADC 82
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#define RESET_BT 83
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/* 84-87 */
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#define RESET_ACODEC 88
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#define RESET_CEC 89
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#define RESET_AFIFO 90
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#define RESET_WATCHDOG 91
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/* 92-95 */
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/* RESET3 */
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#define RESET_BRG_NIC1_GPV 96
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#define RESET_BRG_NIC2_GPV 97
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#define RESET_BRG_NIC3_GPV 98
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#define RESET_BRG_NIC4_GPV 99
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#define RESET_BRG_NIC5_GPV 100
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/* 101-121 */
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#define RESET_MIPI_ISP 122
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#define RESET_BRG_ADB_MALI_1 123
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#define RESET_BRG_ADB_MALI_0 124
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#define RESET_BRG_ADB_A73 125
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#define RESET_BRG_ADB_A53 126
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#define RESET_BRG_CCI 127
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/* RESET4 */
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#define RESET_PWM_AO_AB 128
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#define RESET_PWM_AO_CD 129
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#define RESET_PWM_AO_EF 130
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#define RESET_PWM_AO_GH 131
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#define RESET_PWM_AB 132
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#define RESET_PWM_CD 133
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#define RESET_PWM_EF 134
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/* 135-137 */
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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#define RESET_UART_D 141
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#define RESET_UART_E 142
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#define RESET_UART_F 143
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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#define RESET_I2C_M_E 149
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#define RESET_I2C_M_F 150
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#define RESET_I2C_M_AO_A 151
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#define RESET_SD_EMMC_A 152
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#define RESET_SD_EMMC_B 153
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#define RESET_SD_EMMC_C 154
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#define RESET_I2C_M_AO_B 155
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#define RESET_TS_GPU 156
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#define RESET_TS_NNA 157
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#define RESET_TS_VPN 158
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#define RESET_TS_HEVC 159
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/* RESET5 */
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#define RESET_BRG_NOC_DDR_1 160
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#define RESET_BRG_NOC_DDR_0 161
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#define RESET_BRG_NOC_MAIN 162
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#define RESET_BRG_NOC_ALL 163
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/* 164-167 */
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#define RESET_BRG_NIC2_SYS 168
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#define RESET_BRG_NIC2_MAIN 169
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#define RESET_BRG_NIC2_HDMI 170
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#define RESET_BRG_NIC2_ALL 171
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#define RESET_BRG_NIC3_WAVE 172
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#define RESET_BRG_NIC3_VDEC 173
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#define RESET_BRG_NIC3_HEVCF 174
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#define RESET_BRG_NIC3_HEVCB 175
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#define RESET_BRG_NIC3_HCODEC 176
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#define RESET_BRG_NIC3_GE2D 177
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#define RESET_BRG_NIC3_GDC 178
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#define RESET_BRG_NIC3_AMLOGIC 179
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#define RESET_BRG_NIC3_MAIN 180
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#define RESET_BRG_NIC3_ALL 181
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#define RESET_BRG_NIC5_VPU 182
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/* 183-185 */
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#define RESET_BRG_NIC4_DSPB 186
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#define RESET_BRG_NIC4_DSPA 187
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#define RESET_BRG_NIC4_VAPB 188
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#define RESET_BRG_NIC4_CLK81 189
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#define RESET_BRG_NIC4_MAIN 190
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#define RESET_BRG_NIC4_ALL 191
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/* RESET6 */
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#define RESET_BRG_VDEC_PIPEL 192
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#define RESET_BRG_HEVCF_DMC_PIPEL 193
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#define RESET_BRG_NIC2TONIC4_PIPEL 194
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#define RESET_BRG_HDMIRXTONIC2_PIPEL 195
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#define RESET_BRG_SECTONIC4_PIPEL 196
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#define RESET_BRG_VPUTONOC_PIPEL 197
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#define RESET_BRG_NIC4TONOC_PIPEL 198
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#define RESET_BRG_NIC3TONOC_PIPEL 199
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#define RESET_BRG_NIC2TONOC_PIPEL 200
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#define RESET_BRG_NNATONOC_PIPEL 201
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#define RESET_BRG_FRISP3_PIPEL 202
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#define RESET_BRG_FRISP2_PIPEL 203
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#define RESET_BRG_FRISP1_PIPEL 204
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#define RESET_BRG_FRISP0_PIPEL 205
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/* 206-217 */
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#define RESET_BRG_AMPIPE_NAND 218
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#define RESET_BRG_AMPIPE_ETH 219
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/* 220 */
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#define RESET_BRG_AM2AXI0 221
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#define RESET_BRG_AM2AXI1 222
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#define RESET_BRG_AM2AXI2 223
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#endif /* ___DTS_AMLOGIC_T7_RESET_H */

‎arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi

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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/amlogic,t7-pwrc.h>
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#include "amlogic-t7-reset.h"
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/ {
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interrupt-parent = <&gic>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
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reset: reset-controller@2000 {
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compatible = "amlogic,t7-reset";
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reg = <0x0 0x2000 0x0 0x98>;
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#reset-cells = <1>;
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};
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watchdog@2100 {
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compatible = "amlogic,t7-wdt";
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reg = <0x0 0x2100 0x0 0x10>;

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