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torvaldstorvalds
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Merge tag 'phy-fixes-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul: - Qualcomm QMP driver fixes for missing register offsets and correct N4 offsets for registers * tag 'phy-fixes-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsets phy: qcom-qmp: pcs: Add missing v6 N4 register offsets phy: qcom-qmp: qserdes-txrx: Add missing registers offsets
2 parents d512d02 + 163c1a3 commit a21b52a

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4 files changed

+207
-29
lines changed

4 files changed

+207
-29
lines changed

‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c

Lines changed: 160 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,31 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
187187
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
188188
};
189189

190+
static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
191+
[QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET,
192+
[QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL,
193+
[QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1,
194+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL,
195+
196+
/* In PCS_USB */
197+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
198+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
199+
200+
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
201+
[QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
202+
[QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
203+
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
204+
205+
[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
206+
[QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
207+
208+
[QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV,
209+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL,
210+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL,
211+
[QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN,
212+
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
213+
};
214+
190215
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
191216
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
192217
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -997,6 +1022,31 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
9971022
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
9981023
};
9991024

1025+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = {
1026+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1027+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1028+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1029+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1030+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1031+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1032+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1033+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1034+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1035+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1036+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1037+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1038+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1039+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1040+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1041+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1042+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1043+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1044+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1045+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1046+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1047+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1048+
};
1049+
10001050
static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
10011051
QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
10021052
QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
@@ -1011,6 +1061,19 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
10111061
QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
10121062
};
10131063

1064+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = {
1065+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40),
1066+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00),
1067+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff),
1068+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f),
1069+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03),
1070+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f),
1071+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1072+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1073+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1074+
QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1),
1075+
};
1076+
10141077
static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
10151078
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
10161079
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
@@ -1059,6 +1122,74 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
10591122
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
10601123
};
10611124

1125+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = {
1126+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1127+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1128+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1129+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1130+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1131+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1132+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1133+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1134+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1135+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1136+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1137+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1138+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1139+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1140+
};
1141+
1142+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = {
1143+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1144+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1145+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1146+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1147+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1148+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1149+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1150+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1151+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1152+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1153+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1154+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1155+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1156+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1157+
};
1158+
1159+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = {
1160+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1161+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1162+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1163+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1164+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1165+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1166+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1167+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1168+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1169+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1170+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1171+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1172+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18),
1173+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02),
1174+
};
1175+
1176+
static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = {
1177+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1178+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1179+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1180+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1181+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1182+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1183+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1184+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1185+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1186+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1187+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1188+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1189+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1190+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1191+
};
1192+
10621193
static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
10631194
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
10641195
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
@@ -1273,20 +1404,20 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
12731404
};
12741405

12751406
static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1276-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1277-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1278-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1279-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
1280-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
1281-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
1282-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
1283-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55),
1284-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
1285-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1286-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1287-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
1288-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
1289-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
1407+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1408+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1409+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1410+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89),
1411+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1412+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1413+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1414+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55),
1415+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a),
1416+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1417+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1418+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1419+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b),
1420+
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
12901421
};
12911422

12921423
static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
@@ -1794,22 +1925,22 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
17941925
.pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl,
17951926
.pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
17961927

1797-
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1798-
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1799-
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
1800-
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1928+
.dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl,
1929+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl),
1930+
.dp_tx_tbl = qmp_v6_n4_dp_tx_tbl,
1931+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl),
18011932

1802-
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1803-
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1804-
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1805-
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1806-
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1807-
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1808-
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1809-
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1933+
.serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr,
1934+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr),
1935+
.serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr,
1936+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr),
1937+
.serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2,
1938+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2),
1939+
.serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3,
1940+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3),
18101941

1811-
.swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1812-
.pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1942+
.swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
1943+
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
18131944
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
18141945
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
18151946

@@ -1822,7 +1953,7 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
18221953
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
18231954
.vreg_list = qmp_phy_vreg_l,
18241955
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1825-
.regs = qmp_v45_usb3phy_regs_layout,
1956+
.regs = qmp_v6_n4_usb3phy_regs_layout,
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};
18271958

18281959
static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_V6_N4_H_
7+
#define QCOM_PHY_QMP_PCS_V6_N4_H_
8+
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/* Only for QMP V6 N4 PHY - USB/PCIe PCS registers */
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#define QPHY_V6_N4_PCS_SW_RESET 0x000
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#define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
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#define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
13+
#define QPHY_V6_N4_PCS_START_CONTROL 0x044
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#define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
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#define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V6_N4_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_V6_N4_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V6_N4_PCS_RX_CONFIG 0x1b0
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#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_V6_N4_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_V6_N4_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V6_N4_PCS_EQ_CONFIG5 0x1ec
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#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h

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Original file line numberDiff line numberDiff line change
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
88

9+
#define QSERDES_V6_N4_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL 0x0c
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#define QSERDES_V6_N4_TX_TX_DRV_LVL 0x14
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#define QSERDES_V6_N4_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34
16+
#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN 0x48
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#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN 0x4c
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#define QSERDES_V6_N4_TX_TX_POL_INV 0x50
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#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN 0x54
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#define QSERDES_V6_N4_TX_LANE_MODE_1 0x78
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#define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c
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#define QSERDES_V6_N4_TX_LANE_MODE_3 0x80
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#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN 0xac
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#define QSERDES_V6_N4_TX_TX_BAND 0xd8
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#define QSERDES_V6_N4_TX_INTERFACE_SELECT 0xe4
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#define QSERDES_V6_N4_TX_VMODE_CTRL1 0xb0
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#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8
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#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18

‎drivers/phy/qualcomm/phy-qcom-qmp.h

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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6-n4.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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#include "phy-qcom-qmp-pcs-v7.h"

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