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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add thermal (TSU) clock, reset, and power domain on Renesas RZ/G3S - Add AI accelerator (DRP-AI) clocks and reset on Renesas RZ/V2L - Add Image Signal Processor (ISP, FCPVX, VSPX) clocks on Renesas R-Car V3U V4H, and V4M - Add Watchdog (WDT), SDHI, Interrupt Controller (ICU), Camera (CRU0) and CAN-FD clocks and resets on Renesas RZ/G3E * tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks clk: renesas: r8a779a0: Add FCPVX clocks clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation
2 parents 2014c95 + 9b12504 commit a0e2025

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10 files changed

+242
-60
lines changed

10 files changed

+242
-60
lines changed

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
138138
};
139139

140140
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
141+
DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1),
142+
DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1),
143+
DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1),
144+
DEF_MOD("isp3", 19, R8A779A0_CLK_S1D1),
141145
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
142146
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
143147
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
@@ -238,6 +242,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
238242
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
239243
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
240244
DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
245+
DEF_MOD("fcpvx0", 1100, R8A779A0_CLK_S1D1),
246+
DEF_MOD("fcpvx1", 1101, R8A779A0_CLK_S1D1),
247+
DEF_MOD("fcpvx2", 1102, R8A779A0_CLK_S1D1),
248+
DEF_MOD("fcpvx3", 1103, R8A779A0_CLK_S1D1),
241249
};
242250

243251
static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
163163
};
164164

165165
static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
166+
DEF_MOD("isp0", 16, R8A779G0_CLK_S0D2_VIO),
167+
DEF_MOD("isp1", 17, R8A779G0_CLK_S0D2_VIO),
166168
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
167169
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
168170
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),

‎drivers/clk/renesas/r8a779h0-cpg-mssr.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
171171
};
172172

173173
static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
174+
DEF_MOD("isp0", 16, R8A779H0_CLK_S0D2_VIO),
174175
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
175176
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
176177
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
@@ -238,6 +239,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
238239
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
239240
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
240241
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
242+
DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D1_VIO),
243+
DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D1_VIO),
241244
DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
242245
DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
243246
};

‎drivers/clk/renesas/r9a07g043-cpg.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,9 @@ static const struct clk_div_table dtable_1_32[] = {
8989

9090
/* Mux clock tables */
9191
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
92+
#ifdef CONFIG_ARM64
9293
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
94+
#endif
9395
static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
9496

9597
static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -137,7 +139,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
137139
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
138140
DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
139141
DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
142+
#ifdef CONFIG_ARM64
140143
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
144+
#endif
145+
#ifdef CONFIG_RISCV
146+
DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),
147+
#endif
141148
DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
142149
DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
143150
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 53 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,41 @@ static const struct clk_div_table dtable_1_32[] = {
9494
{0, 0},
9595
};
9696

97+
#ifdef CONFIG_CLK_R9A07G054
98+
static const struct clk_div_table dtable_4_32[] = {
99+
{3, 4},
100+
{4, 5},
101+
{5, 6},
102+
{6, 7},
103+
{7, 8},
104+
{8, 9},
105+
{9, 10},
106+
{10, 11},
107+
{11, 12},
108+
{12, 13},
109+
{13, 14},
110+
{14, 15},
111+
{15, 16},
112+
{16, 17},
113+
{17, 18},
114+
{18, 19},
115+
{19, 20},
116+
{20, 21},
117+
{21, 22},
118+
{22, 23},
119+
{23, 24},
120+
{24, 25},
121+
{25, 26},
122+
{26, 27},
123+
{27, 28},
124+
{28, 29},
125+
{29, 30},
126+
{30, 31},
127+
{31, 32},
128+
{0, 0},
129+
};
130+
#endif
131+
97132
static const struct clk_div_table dtable_16_128[] = {
98133
{0, 16},
99134
{1, 32},
@@ -114,7 +149,7 @@ static const u32 mtable_sdhi[] = { 1, 2, 3 };
114149
static const struct {
115150
struct cpg_core_clk common[56];
116151
#ifdef CONFIG_CLK_R9A07G054
117-
struct cpg_core_clk drp[0];
152+
struct cpg_core_clk drp[3];
118153
#endif
119154
} core_clks __initconst = {
120155
.common = {
@@ -192,14 +227,17 @@ static const struct {
192227
},
193228
#ifdef CONFIG_CLK_R9A07G054
194229
.drp = {
230+
DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5),
231+
DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2),
232+
DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32),
195233
},
196234
#endif
197235
};
198236

199237
static const struct {
200238
struct rzg2l_mod_clk common[79];
201239
#ifdef CONFIG_CLK_R9A07G054
202-
struct rzg2l_mod_clk drp[0];
240+
struct rzg2l_mod_clk drp[5];
203241
#endif
204242
} mod_clks = {
205243
.common = {
@@ -364,6 +402,16 @@ static const struct {
364402
},
365403
#ifdef CONFIG_CLK_R9A07G054
366404
.drp = {
405+
DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,
406+
0x5e8, 0),
407+
DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,
408+
0x5e8, 1),
409+
DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,
410+
0x5e8, 2),
411+
DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,
412+
0x5e8, 3),
413+
DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,
414+
0x5e8, 4),
367415
},
368416
#endif
369417
};
@@ -430,6 +478,9 @@ static const struct rzg2l_reset r9a07g044_resets[] = {
430478
DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
431479
DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
432480
DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
481+
#ifdef CONFIG_CLK_R9A07G054
482+
DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0),
483+
#endif
433484
};
434485

435486
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
5252

5353
/* PLL 1/4/6 configuration registers macro. */
54-
#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
54+
#define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting))
5555

5656
#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
5757
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
@@ -134,7 +134,8 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
134134

135135
/* Internal Core Clocks */
136136
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
137-
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
137+
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
138+
1100000000UL),
138139
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
139140
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
140141
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
@@ -241,6 +242,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
241242
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
242243
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
243244
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
245+
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0),
244246
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
245247
};
246248

@@ -279,6 +281,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
279281
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
280282
DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
281283
DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
284+
DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
282285
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
283286
};
284287

@@ -353,6 +356,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
353356
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
354357
DEF_PD("adc", R9A08G045_PD_ADC,
355358
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
359+
DEF_PD("tsu", R9A08G045_PD_TSU,
360+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0),
356361
DEF_PD("vbat", R9A08G045_PD_VBAT,
357362
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
358363
GENPD_FLAG_ALWAYS_ON),

‎drivers/clk/renesas/r9a09g047-cpg.c

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,19 @@ enum clk_ids {
2828
CLK_PLLCLN,
2929
CLK_PLLDTY,
3030
CLK_PLLCA55,
31+
CLK_PLLVDO,
3132

3233
/* Internal Core Clocks */
3334
CLK_PLLCM33_DIV16,
35+
CLK_PLLCLN_DIV2,
36+
CLK_PLLCLN_DIV8,
3437
CLK_PLLCLN_DIV16,
38+
CLK_PLLCLN_DIV20,
3539
CLK_PLLDTY_ACPU,
40+
CLK_PLLDTY_ACPU_DIV2,
3641
CLK_PLLDTY_ACPU_DIV4,
42+
CLK_PLLDTY_DIV16,
43+
CLK_PLLVDO_CRU0,
3744

3845
/* Module Clocks */
3946
MOD_CLK_BASE,
@@ -47,6 +54,12 @@ static const struct clk_div_table dtable_1_8[] = {
4754
{0, 0},
4855
};
4956

57+
static const struct clk_div_table dtable_2_4[] = {
58+
{0, 2},
59+
{1, 4},
60+
{0, 0},
61+
};
62+
5063
static const struct clk_div_table dtable_2_64[] = {
5164
{0, 2},
5265
{1, 4},
@@ -67,14 +80,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
6780
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
6881
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
6982
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
83+
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
7084

7185
/* Internal Core Clocks */
7286
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
7387

88+
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
89+
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
7490
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
91+
DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
7592

7693
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
94+
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
7795
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
96+
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
97+
98+
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
7899

79100
/* Core Clocks */
80101
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -90,8 +111,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
90111
};
91112

92113
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
114+
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
115+
BUS_MSTOP_NONE),
93116
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
94117
BUS_MSTOP(3, BIT(5))),
118+
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
119+
BUS_MSTOP(1, BIT(0))),
120+
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
121+
BUS_MSTOP(1, BIT(0))),
122+
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
123+
BUS_MSTOP(5, BIT(12))),
124+
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
125+
BUS_MSTOP(5, BIT(12))),
126+
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
127+
BUS_MSTOP(5, BIT(13))),
128+
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
129+
BUS_MSTOP(5, BIT(13))),
95130
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
96131
BUS_MSTOP(3, BIT(14))),
97132
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -112,12 +147,52 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
112147
BUS_MSTOP(1, BIT(7))),
113148
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
114149
BUS_MSTOP(1, BIT(8))),
150+
DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
151+
BUS_MSTOP(10, BIT(14))),
152+
DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
153+
BUS_MSTOP(10, BIT(14))),
154+
DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
155+
BUS_MSTOP(10, BIT(14))),
156+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
157+
BUS_MSTOP(8, BIT(2))),
158+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
159+
BUS_MSTOP(8, BIT(2))),
160+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
161+
BUS_MSTOP(8, BIT(2))),
162+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
163+
BUS_MSTOP(8, BIT(2))),
164+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
165+
BUS_MSTOP(8, BIT(3))),
166+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
167+
BUS_MSTOP(8, BIT(3))),
168+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
169+
BUS_MSTOP(8, BIT(3))),
170+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
171+
BUS_MSTOP(8, BIT(3))),
172+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
173+
BUS_MSTOP(8, BIT(4))),
174+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
175+
BUS_MSTOP(8, BIT(4))),
176+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
177+
BUS_MSTOP(8, BIT(4))),
178+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
179+
BUS_MSTOP(8, BIT(4))),
180+
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
181+
BUS_MSTOP(9, BIT(4))),
182+
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
183+
BUS_MSTOP(9, BIT(4))),
184+
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
185+
BUS_MSTOP(9, BIT(4))),
115186
};
116187

117188
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
118189
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
190+
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
119191
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
120192
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
193+
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
194+
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
195+
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
121196
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
122197
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
123198
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
@@ -128,6 +203,14 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
128203
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
129204
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
130205
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
206+
DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
207+
DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
208+
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
209+
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
210+
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
211+
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
212+
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
213+
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
131214
};
132215

133216
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {

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