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airliedairlied
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Merge tag 'drm-intel-next-2024-04-30' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-next
Core DRM: - Export drm_client_dev_unregister (Thomas Zimmermann) Display i915: - More initial work to make display code more independent from i915 (Jani) - Convert i915/xe fbdev to DRM client (Thomas Zimmermann) - VLV/CHV DPIO register cleanup (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZjFPcSCTd_5c0XU_@intel.com
2 parents 4a56c0e + 6f1923f commit 9f9039c

31 files changed

+1406
-1457
lines changed

‎drivers/gpu/drm/drm_client.c

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,18 @@ void drm_client_release(struct drm_client_dev *client)
172172
}
173173
EXPORT_SYMBOL(drm_client_release);
174174

175+
/**
176+
* drm_client_dev_unregister - Unregister clients
177+
* @dev: DRM device
178+
*
179+
* This function releases all clients by calling each client's
180+
* &drm_client_funcs.unregister callback. The callback function
181+
* is responsibe for releaseing all resources including the client
182+
* itself.
183+
*
184+
* The helper drm_dev_unregister() calls this function. Drivers
185+
* that use it don't need to call this function themselves.
186+
*/
175187
void drm_client_dev_unregister(struct drm_device *dev)
176188
{
177189
struct drm_client_dev *client, *tmp;
@@ -191,6 +203,7 @@ void drm_client_dev_unregister(struct drm_device *dev)
191203
}
192204
mutex_unlock(&dev->clientlist_mutex);
193205
}
206+
EXPORT_SYMBOL(drm_client_dev_unregister);
194207

195208
/**
196209
* drm_client_dev_hotplug - Send hotplug event to clients

‎drivers/gpu/drm/i915/display/intel_audio_regs.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,4 +148,20 @@
148148
#define HBLANK_START_COUNT_96 4
149149
#define HBLANK_START_COUNT_128 5
150150

151+
/* LPE Audio */
152+
#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
153+
#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
154+
155+
#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
156+
#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
157+
158+
#define _VLV_AUD_PORT_EN_B_DBG 0x62F20
159+
#define _VLV_AUD_PORT_EN_C_DBG 0x62F30
160+
#define _VLV_AUD_PORT_EN_D_DBG 0x62F34
161+
#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
162+
_VLV_AUD_PORT_EN_B_DBG, \
163+
_VLV_AUD_PORT_EN_C_DBG, \
164+
_VLV_AUD_PORT_EN_D_DBG)
165+
#define VLV_AMP_MUTE (1 << 1)
166+
151167
#endif /* __INTEL_AUDIO_REGS_H__ */

‎drivers/gpu/drm/i915/display/intel_color.c

Lines changed: 31 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -616,19 +616,19 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc,
616616
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
617617
enum pipe pipe = crtc->pipe;
618618

619-
intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
619+
intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe),
620620
csc->coeff[1] << 16 | csc->coeff[0]);
621-
intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
621+
intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe),
622622
csc->coeff[2]);
623623

624-
intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
624+
intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe),
625625
csc->coeff[4] << 16 | csc->coeff[3]);
626-
intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
626+
intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe),
627627
csc->coeff[5]);
628628

629-
intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
629+
intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe),
630630
csc->coeff[7] << 16 | csc->coeff[6]);
631-
intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
631+
intel_de_write_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe),
632632
csc->coeff[8]);
633633
}
634634

@@ -639,25 +639,25 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc,
639639
enum pipe pipe = crtc->pipe;
640640
u32 tmp;
641641

642-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
642+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe));
643643
csc->coeff[0] = tmp & 0xffff;
644644
csc->coeff[1] = tmp >> 16;
645645

646-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
646+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe));
647647
csc->coeff[2] = tmp & 0xffff;
648648

649-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
649+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe));
650650
csc->coeff[3] = tmp & 0xffff;
651651
csc->coeff[4] = tmp >> 16;
652652

653-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
653+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe));
654654
csc->coeff[5] = tmp & 0xffff;
655655

656-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
656+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe));
657657
csc->coeff[6] = tmp & 0xffff;
658658
csc->coeff[7] = tmp >> 16;
659659

660-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
660+
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe));
661661
csc->coeff[8] = tmp & 0xffff;
662662
}
663663

@@ -1227,7 +1227,7 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc,
12271227
lut = blob->data;
12281228

12291229
for (i = 0; i < 256; i++)
1230-
intel_de_write_fw(dev_priv, PALETTE(pipe, i),
1230+
intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i),
12311231
i9xx_lut_8(&lut[i]));
12321232
}
12331233

@@ -1240,9 +1240,11 @@ static void i9xx_load_lut_10(struct intel_crtc *crtc,
12401240
enum pipe pipe = crtc->pipe;
12411241

12421242
for (i = 0; i < lut_size - 1; i++) {
1243-
intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
1243+
intel_de_write_fw(dev_priv,
1244+
PALETTE(dev_priv, pipe, 2 * i + 0),
12441245
i9xx_lut_10_ldw(&lut[i]));
1245-
intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
1246+
intel_de_write_fw(dev_priv,
1247+
PALETTE(dev_priv, pipe, 2 * i + 1),
12461248
i9xx_lut_10_udw(&lut[i]));
12471249
}
12481250
}
@@ -1274,9 +1276,11 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
12741276
enum pipe pipe = crtc->pipe;
12751277

12761278
for (i = 0; i < lut_size - 1; i++) {
1277-
intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
1279+
intel_de_write_fw(dev_priv,
1280+
PALETTE(dev_priv, pipe, 2 * i + 0),
12781281
i965_lut_10p6_ldw(&lut[i]));
1279-
intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
1282+
intel_de_write_fw(dev_priv,
1283+
PALETTE(dev_priv, pipe, 2 * i + 1),
12801284
i965_lut_10p6_udw(&lut[i]));
12811285
}
12821286

@@ -3150,7 +3154,8 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
31503154
lut = blob->data;
31513155

31523156
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
3153-
u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i));
3157+
u32 val = intel_de_read_fw(dev_priv,
3158+
PALETTE(dev_priv, pipe, i));
31543159

31553160
i9xx_lut_8_pack(&lut[i], val);
31563161
}
@@ -3176,8 +3181,10 @@ static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
31763181
lut = blob->data;
31773182

31783183
for (i = 0; i < lut_size - 1; i++) {
3179-
ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
3180-
udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
3184+
ldw = intel_de_read_fw(dev_priv,
3185+
PALETTE(dev_priv, pipe, 2 * i + 0));
3186+
udw = intel_de_read_fw(dev_priv,
3187+
PALETTE(dev_priv, pipe, 2 * i + 1));
31813188

31823189
i9xx_lut_10_pack(&lut[i], ldw, udw);
31833190
}
@@ -3224,8 +3231,10 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
32243231
lut = blob->data;
32253232

32263233
for (i = 0; i < lut_size - 1; i++) {
3227-
u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
3228-
u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
3234+
u32 ldw = intel_de_read_fw(dev_priv,
3235+
PALETTE(dev_priv, pipe, 2 * i + 0));
3236+
u32 udw = intel_de_read_fw(dev_priv,
3237+
PALETTE(dev_priv, pipe, 2 * i + 1));
32293238

32303239
i965_lut_10p6_pack(&lut[i], ldw, udw);
32313240
}

‎drivers/gpu/drm/i915/display/intel_color_regs.h

Lines changed: 35 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,35 @@
88

99
#include "intel_display_reg_defs.h"
1010

11-
/* legacy palette */
11+
/* GMCH palette */
12+
#define _PALETTE_A 0xa000
13+
#define _PALETTE_B 0xa800
14+
#define _CHV_PALETTE_C 0xc000
15+
/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
16+
#define PALETTE_RED_MASK REG_GENMASK(23, 16)
17+
#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
18+
#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
19+
/* pre-i965 10bit interpolated mode ldw */
20+
#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
21+
#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
22+
#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
23+
/* pre-i965 10bit interpolated mode udw */
24+
#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
25+
#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
26+
#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
27+
#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
28+
#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
29+
#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
30+
#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
31+
#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
32+
#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
33+
#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
34+
_PICK_EVEN_2RANGES(pipe, 2, \
35+
_PALETTE_A, _PALETTE_B, \
36+
_CHV_PALETTE_C, _CHV_PALETTE_C) + \
37+
(i) * 4)
38+
39+
/* ilk+ palette */
1240
#define _LGC_PALETTE_A 0x4a000
1341
#define _LGC_PALETTE_B 0x4a800
1442
/* see PALETTE_* for the bits */
@@ -228,12 +256,12 @@
228256
#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
229257
#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
230258

231-
#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
232-
#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
233-
#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
234-
#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
235-
#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
236-
#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
259+
#define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)
260+
#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
261+
#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)
262+
#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
263+
#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)
264+
#define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)
237265

238266
/* pipe CSC & degamma/gamma LUTs on CHV */
239267
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@
8585
#include "intel_dvo.h"
8686
#include "intel_fb.h"
8787
#include "intel_fbc.h"
88-
#include "intel_fbdev.h"
8988
#include "intel_fdi.h"
9089
#include "intel_fifo_underrun.h"
9190
#include "intel_frontbuffer.h"
@@ -120,6 +119,7 @@
120119
#include "skl_scaler.h"
121120
#include "skl_universal_plane.h"
122121
#include "skl_watermark.h"
122+
#include "vlv_dpio_phy_regs.h"
123123
#include "vlv_dsi.h"
124124
#include "vlv_dsi_pll.h"
125125
#include "vlv_dsi_regs.h"

‎drivers/gpu/drm/i915/display/intel_display_driver.c

Lines changed: 5 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <acpi/video.h>
1212
#include <drm/display/drm_dp_mst_helper.h>
1313
#include <drm/drm_atomic_helper.h>
14+
#include <drm/drm_client.h>
1415
#include <drm/drm_mode_config.h>
1516
#include <drm/drm_privacy_screen_consumer.h>
1617
#include <drm/drm_probe_helper.h>
@@ -98,7 +99,6 @@ void intel_display_driver_init_hw(struct drm_i915_private *i915)
9899
static const struct drm_mode_config_funcs intel_mode_funcs = {
99100
.fb_create = intel_user_framebuffer_create,
100101
.get_format_info = intel_fb_get_format_info,
101-
.output_poll_changed = intel_fbdev_output_poll_changed,
102102
.mode_valid = intel_mode_valid,
103103
.atomic_check = intel_atomic_check,
104104
.atomic_commit = intel_atomic_commit,
@@ -516,10 +516,6 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
516516

517517
intel_overlay_setup(i915);
518518

519-
ret = intel_fbdev_init(&i915->drm);
520-
if (ret)
521-
return ret;
522-
523519
/* Only enable hotplug handling once the fbdev is fully set up. */
524520
intel_hpd_init(i915);
525521

@@ -546,16 +542,6 @@ void intel_display_driver_register(struct drm_i915_private *i915)
546542

547543
intel_display_debugfs_register(i915);
548544

549-
/*
550-
* Some ports require correctly set-up hpd registers for
551-
* detection to work properly (leading to ghost connected
552-
* connector status), e.g. VGA on gm45. Hence we can only set
553-
* up the initial fbdev config after hpd irqs are fully
554-
* enabled. We do it last so that the async config cannot run
555-
* before the connectors are registered.
556-
*/
557-
intel_fbdev_initial_config_async(i915);
558-
559545
/*
560546
* We need to coordinate the hotplugs with the asynchronous
561547
* fbdev configuration, for which we use the
@@ -564,6 +550,8 @@ void intel_display_driver_register(struct drm_i915_private *i915)
564550
drm_kms_helper_poll_init(&i915->drm);
565551
intel_hpd_poll_disable(i915);
566552

553+
intel_fbdev_setup(i915);
554+
567555
intel_display_device_info_print(DISPLAY_INFO(i915),
568556
DISPLAY_RUNTIME_INFO(i915), &p);
569557
}
@@ -599,9 +587,6 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
599587
*/
600588
intel_hpd_poll_fini(i915);
601589

602-
/* poll work can call into fbdev, hence clean that up afterwards */
603-
intel_fbdev_fini(i915);
604-
605590
intel_unregister_dsm_handler();
606591

607592
/* flush any delayed tasks or pending work */
@@ -640,7 +625,8 @@ void intel_display_driver_unregister(struct drm_i915_private *i915)
640625
if (!HAS_DISPLAY(i915))
641626
return;
642627

643-
intel_fbdev_unregister(i915);
628+
drm_client_dev_unregister(&i915->drm);
629+
644630
/*
645631
* After flushing the fbdev (incl. a late async config which
646632
* will have delayed queuing of a hotplug event), then flush

‎drivers/gpu/drm/i915/display/intel_display_power_well.c

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include "intel_tc.h"
2828
#include "intel_vga.h"
2929
#include "skl_watermark.h"
30+
#include "vlv_dpio_phy_regs.h"
3031
#include "vlv_sideband.h"
3132
#include "vlv_sideband_reg.h"
3233

@@ -1442,9 +1443,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
14421443
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
14431444

14441445
if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1445-
tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);
1446+
tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
14461447
tmp |= DPIO_DYNPWRDOWNEN_CH1;
1447-
vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);
1448+
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
14481449
} else {
14491450
/*
14501451
* Force the non-existing CL2 off. BXT does this
@@ -1520,9 +1521,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
15201521
return;
15211522

15221523
if (ch == DPIO_CH0)
1523-
reg = _CHV_CMN_DW0_CH0;
1524+
reg = CHV_CMN_DW0_CH0;
15241525
else
1525-
reg = _CHV_CMN_DW6_CH1;
1526+
reg = CHV_CMN_DW6_CH1;
15261527

15271528
vlv_dpio_get(dev_priv);
15281529
val = vlv_dpio_read(dev_priv, phy, reg);
@@ -1553,10 +1554,11 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
15531554
}
15541555

15551556
if (ch == DPIO_CH0)
1556-
actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1557+
actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |
1558+
DPIO_ALLDL_POWERDOWN_CH0, val);
15571559
else
1558-
actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1559-
actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1560+
actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |
1561+
DPIO_ALLDL_POWERDOWN_CH1, val);
15601562

15611563
drm_WARN(&dev_priv->drm, actual != expected,
15621564
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",

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