|
193 | 193 | status = "disabled";
|
194 | 194 | };
|
195 | 195 |
|
| 196 | + emmc: mmc@ffe7080000 { |
| 197 | + compatible = "thead,th1520-dwcmshc"; |
| 198 | + reg = <0xff 0xe7080000 0x0 0x10000>; |
| 199 | + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; |
| 200 | + clocks = <&sdhci_clk>; |
| 201 | + clock-names = "core"; |
| 202 | + status = "disabled"; |
| 203 | + }; |
| 204 | + |
| 205 | + sdio0: mmc@ffe7090000 { |
| 206 | + compatible = "thead,th1520-dwcmshc"; |
| 207 | + reg = <0xff 0xe7090000 0x0 0x10000>; |
| 208 | + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; |
| 209 | + clocks = <&sdhci_clk>; |
| 210 | + clock-names = "core"; |
| 211 | + status = "disabled"; |
| 212 | + }; |
| 213 | + |
| 214 | + sdio1: mmc@ffe70a0000 { |
| 215 | + compatible = "thead,th1520-dwcmshc"; |
| 216 | + reg = <0xff 0xe70a0000 0x0 0x10000>; |
| 217 | + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; |
| 218 | + clocks = <&sdhci_clk>; |
| 219 | + clock-names = "core"; |
| 220 | + status = "disabled"; |
| 221 | + }; |
| 222 | + |
196 | 223 | uart1: serial@ffe7f00000 {
|
197 | 224 | compatible = "snps,dw-apb-uart";
|
198 | 225 | reg = <0xff 0xe7f00000 0x0 0x100>;
|
|
311 | 338 | status = "disabled";
|
312 | 339 | };
|
313 | 340 |
|
314 |
| - emmc: mmc@ffe7080000 { |
315 |
| - compatible = "thead,th1520-dwcmshc"; |
316 |
| - reg = <0xff 0xe7080000 0x0 0x10000>; |
317 |
| - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; |
318 |
| - clocks = <&sdhci_clk>; |
319 |
| - clock-names = "core"; |
320 |
| - status = "disabled"; |
321 |
| - }; |
322 |
| - |
323 |
| - sdio0: mmc@ffe7090000 { |
324 |
| - compatible = "thead,th1520-dwcmshc"; |
325 |
| - reg = <0xff 0xe7090000 0x0 0x10000>; |
326 |
| - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; |
327 |
| - clocks = <&sdhci_clk>; |
328 |
| - clock-names = "core"; |
329 |
| - status = "disabled"; |
330 |
| - }; |
331 |
| - |
332 |
| - sdio1: mmc@ffe70a0000 { |
333 |
| - compatible = "thead,th1520-dwcmshc"; |
334 |
| - reg = <0xff 0xe70a0000 0x0 0x10000>; |
335 |
| - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; |
336 |
| - clocks = <&sdhci_clk>; |
337 |
| - clock-names = "core"; |
338 |
| - status = "disabled"; |
339 |
| - }; |
340 |
| - |
341 | 341 | timer0: timer@ffefc32000 {
|
342 | 342 | compatible = "snps,dw-apb-timer";
|
343 | 343 | reg = <0xff 0xefc32000 0x0 0x14>;
|
|
0 commit comments