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Merge tag 'pwm/for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding: "Quite a large number of conversions this time around, courtesy of Uwe who has been working tirelessly on these. No drivers of the legacy API are left at this point, so as a next step the old API can be removed. Support is added for a few new devices such as the Xilinx AXI timer- based PWMs and the PWM IP found on Sunplus SoCs. Other than that, there's a number of fixes, cleanups and optimizations" * tag 'pwm/for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (43 commits) pwm: pwm-cros-ec: Add channel type support dt-bindings: google,cros-ec-pwm: Add the new -type compatible dt-bindings: Add mfd/cros_ec definitions pwm: Document that the pinstate of a disabled PWM isn't reliable pwm: twl-led: Implement .apply() callback pwm: lpc18xx: Implement .apply() callback pwm: mediatek: Implement .apply() callback pwm: lpc32xx: Implement .apply() callback pwm: tegra: Implement .apply() callback pwm: stmpe: Implement .apply() callback pwm: sti: Implement .apply() callback pwm: pwm-mediatek: Add support for MediaTek Helio X10 MT6795 dt-bindings: pwm: pwm-mediatek: Add documentation for MT6795 SoC pwm: tegra: Optimize period calculation pwm: renesas-tpu: Improve precision of period and duty_cycle calculation pwm: renesas-tpu: Improve maths to compute register settings pwm: renesas-tpu: Rename variables to match the usual naming pwm: renesas-tpu: Implement .apply() callback pwm: renesas-tpu: Make use of devm functions pwm: renesas-tpu: Make use of dev_err_probe() ...
2 parents 68e6134 + 3d593b6 commit 8eca6b0

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‎Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel/Microchip PWM controller
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maintainers:
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- Claudiu Beznea <claudiu.beznea@microchip.com>
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allOf:
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- $ref: "pwm.yaml#"
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- atmel,at91sam9rl-pwm
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- atmel,sama5d3-pwm
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- atmel,sama5d2-pwm
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- microchip,sam9x60-pwm
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- items:
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- const: microchip,sama7g5-pwm
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- const: atmel,sama5d2-pwm
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reg:
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maxItems: 1
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"#pwm-cells":
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const: 3
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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pwm0: pwm@f8034000 {
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compatible = "atmel,at91sam9rl-pwm";
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reg = <0xf8034000 0x400>;
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#pwm-cells = <3>;
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};

‎Documentation/devicetree/bindings/pwm/atmel-pwm.txt

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‎Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml

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properties:
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compatible:
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const: google,cros-ec-pwm
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oneOf:
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- description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
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items:
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- const: google,cros-ec-pwm
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- description: PWM controlled using CROS_EC_PWM_DT_<...> types.
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items:
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- const: google,cros-ec-pwm-type
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"#pwm-cells":
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description: The cell specifies the PWM index.
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const: 1

‎Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek DISP_PWM Controller Device Tree Bindings
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maintainers:
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- Jitao Shi <jitao.shi@mediatek.com>
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- Xinlei Lee <xinlei.lee@mediatek.com>
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-disp-pwm
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- mediatek,mt6595-disp-pwm
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- mediatek,mt8173-disp-pwm
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- mediatek,mt8183-disp-pwm
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- items:
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- const: mediatek,mt8167-disp-pwm
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- const: mediatek,mt8173-disp-pwm
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- items:
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- enum:
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- mediatek,mt8186-disp-pwm
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- mediatek,mt8192-disp-pwm
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- mediatek,mt8195-disp-pwm
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- const: mediatek,mt8183-disp-pwm
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reg:
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maxItems: 1
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"#pwm-cells":
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const: 2
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Main Clock
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- description: Mm Clock
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clock-names:
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items:
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- const: main
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- const: mm
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required:
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- compatible
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- reg
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- "#pwm-cells"
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm";
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reg = <0x1401e000 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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<&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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};

‎Documentation/devicetree/bindings/pwm/pwm-mediatek.txt

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Required properties:
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- compatible: should be "mediatek,<name>-pwm":
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- "mediatek,mt2712-pwm": found on mt2712 SoC.
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- "mediatek,mt6795-pwm": found on mt6795 SoC.
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- "mediatek,mt7622-pwm": found on mt7622 SoC.
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- "mediatek,mt7623-pwm": found on mt7623 SoC.
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- "mediatek,mt7628-pwm": found on mt7628 SoC.

‎Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt

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‎Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) Sunplus Co., Ltd. 2021
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/sunplus,sp7021-pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sunplus SoC SP7021 PWM Controller
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maintainers:
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- Hammer Hsieh <hammerh0314@gmail.com>
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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const: sunplus,sp7021-pwm
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#pwm-cells':
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const: 2
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unevaluatedProperties: false
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required:
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- reg
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- clocks
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examples:
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- |
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pwm: pwm@9c007a00 {
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compatible = "sunplus,sp7021-pwm";
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reg = <0x9c007a00 0x80>;
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clocks = <&clkc 0xa2>;
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#pwm-cells = <2>;
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};

‎Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx LogiCORE IP AXI Timer Device Tree Binding
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maintainers:
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- Sean Anderson <sean.anderson@seco.com>
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properties:
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compatible:
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contains:
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const: xlnx,xps-timer-1.00.a
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clocks:
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maxItems: 1
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clock-names:
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const: s_axi_aclk
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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'#pwm-cells': true
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xlnx,count-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16, 32]
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default: 32
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description:
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The width of the counter(s), in bits.
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xlnx,one-timer-only:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Whether only one timer is present in this block.
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required:
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- compatible
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- reg
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- xlnx,one-timer-only
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allOf:
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- if:
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required:
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- '#pwm-cells'
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then:
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allOf:
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- required:
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- clocks
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- properties:
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xlnx,one-timer-only:
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const: 0
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else:
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required:
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- interrupts
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- if:
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required:
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- clocks
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then:
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required:
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- clock-names
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additionalProperties: false
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examples:
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- |
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timer@800e0000 {
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clock-names = "s_axi_aclk";
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clocks = <&zynqmp_clk 71>;
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x800e0000 0x10000>;
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interrupts = <0 39 2>;
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xlnx,count-width = <16>;
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xlnx,one-timer-only = <0x0>;
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};
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timer@800f0000 {
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#pwm-cells = <0>;
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clock-names = "s_axi_aclk";
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clocks = <&zynqmp_clk 71>;
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x800e0000 0x10000>;
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xlnx,count-width = <32>;
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xlnx,one-timer-only = <0x0>;
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};

‎Documentation/driver-api/pwm.rst

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This API controls both the PWM period/duty_cycle config and the
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enable/disable state.
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As a consumer, don't rely on the output's state for a disabled PWM. If it's
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easily possible, drivers are supposed to emit the inactive state, but some
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drivers cannot. If you rely on getting the inactive state, use .duty_cycle=0,
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.enabled=true.
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There is also a usage_power setting: If set, the PWM driver is only required to
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maintain the power output but has more freedom regarding signal form.
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If supported by the driver, the signal can be optimized, for example to improve

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