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Merge branch 'for-next/perf' into for-next/core
* for-next/perf: (41 commits) arm64: Add USER_STACKTRACE support drivers/perf: hisi: hns3: Actually use devm_add_action_or_reset() drivers/perf: hisi: hns3: Fix out-of-bound access when valid event group drivers/perf: hisi_pcie: Fix out-of-bound access when valid event group perf/arm-spe: Assign parents for event_source device perf/arm-smmuv3: Assign parents for event_source device perf/arm-dsu: Assign parents for event_source device perf/arm-dmc620: Assign parents for event_source device perf/arm-ccn: Assign parents for event_source device perf/arm-cci: Assign parents for event_source device perf/alibaba_uncore: Assign parents for event_source device perf/arm_pmu: Assign parents for event_source devices perf/imx_ddr: Assign parents for event_source devices perf/qcom: Assign parents for event_source devices Documentation: qcom-pmu: Use /sys/bus/event_source/devices paths perf/riscv: Assign parents for event_source devices perf/thunderx2: Assign parents for event_source devices Documentation: thunderx2-pmu: Use /sys/bus/event_source/devices paths perf/xgene: Assign parents for event_source devices Documentation: xgene-pmu: Use /sys/bus/event_source/devices paths ...
2 parents a5a5ce5 + 410e471 commit 42e7ddb

34 files changed

+253
-203
lines changed

Documentation/admin-guide/perf/hisi-pmu.rst

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@@ -20,7 +20,6 @@ interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see:
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23-
/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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The "perf list" command shall list the available events from sysfs.
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Documentation/admin-guide/perf/hns3-pmu.rst

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@@ -16,7 +16,7 @@ HNS3 PMU driver
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The HNS3 PMU driver registers a perf PMU with the name of its sicl id.::
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/sys/devices/hns3_pmu_sicl_<sicl_id>
19+
/sys/bus/event_source/devices/hns3_pmu_sicl_<sicl_id>
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PMU driver provides description of available events, filter modes, format,
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identifier and cpumask in sysfs.
@@ -40,9 +40,9 @@ device.
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Example usage of checking event code and subevent code::
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43-
$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
43+
$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
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config=0x00204
45-
$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
45+
$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
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config=0x10204
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Each performance statistic has a pair of events to get two values to
@@ -60,7 +60,7 @@ computation to calculate real performance data is:::
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Example usage of checking supported filter mode::
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63-
$# cat /sys/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
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$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
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filter mode supported: global/port/port-tc/func/func-queue/
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Example usage of perf::

Documentation/admin-guide/perf/qcom_l2_pmu.rst

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@@ -10,7 +10,7 @@ There is one logical L2 PMU exposed, which aggregates the results from
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the physical PMUs.
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The driver provides a description of its available events and configuration
13-
options in sysfs, see /sys/devices/l2cache_0.
13+
options in sysfs, see /sys/bus/event_source/devices/l2cache_0.
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The "format" directory describes the format of the events.
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Documentation/admin-guide/perf/qcom_l3_pmu.rst

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@@ -9,7 +9,7 @@ PMU with device name l3cache_<socket>_<instance>. User space is responsible
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for aggregating across slices.
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The driver provides a description of its available events and configuration
12-
options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
12+
options in sysfs, see /sys/bus/event_source/devices/l3cache*. Given that these are uncore PMUs
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the driver also exposes a "cpumask" sysfs attribute which contains a mask
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consisting of one CPU per socket which will be used to handle all the PMU
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events on that socket.

Documentation/admin-guide/perf/thunderx2-pmu.rst

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@@ -22,7 +22,7 @@ The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
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L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
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(CCPI2) events simultaneously. The PMUs provide a description of their
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available events and configuration options under sysfs, see
25-
/sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
25+
/sys/bus/event_source/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
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2727
The driver does not support sampling, therefore "perf record" will not
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work. Per-task perf sessions are also not supported.

Documentation/admin-guide/perf/xgene-pmu.rst

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@@ -13,7 +13,7 @@ PMU (perf) driver
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The xgene-pmu driver registers several perf PMU drivers. Each of the perf
1515
driver provides description of its available events and configuration options
16-
in sysfs, see /sys/devices/<l3cX/iobX/mcbX/mcX>/.
16+
in sysfs, see /sys/bus/event_source/devices/<l3cX/iobX/mcbX/mcX>/.
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The "format" directory describes format of the config (event ID),
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config1 (agent ID) fields of the perf_event_attr structure. The "events"

arch/arm64/Kconfig

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@@ -259,6 +259,7 @@ config ARM64
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select TRACE_IRQFLAGS_SUPPORT
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select TRACE_IRQFLAGS_NMI_SUPPORT
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select HAVE_SOFTIRQ_ON_OWN_STACK
262+
select USER_STACKTRACE_SUPPORT
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help
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ARM 64-bit (AArch64) Linux support.
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arch/arm64/include/asm/assembler.h

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@@ -476,9 +476,10 @@ alternative_endif
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*/
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.macro reset_pmuserenr_el0, tmpreg
478478
mrs \tmpreg, id_aa64dfr0_el1
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sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
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cmp \tmpreg, #1 // Skip if no PMU present
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b.lt 9000f
479+
ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
480+
cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI
481+
ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
482+
b.eq 9000f // Skip if no PMU present or IMP_DEF
482483
msr pmuserenr_el0, xzr // Disable PMU access from EL0
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9000:
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.endm

arch/arm64/include/asm/el2_setup.h

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@@ -59,13 +59,14 @@
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.macro __init_el2_debug
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mrs x1, id_aa64dfr0_el1
62-
sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
63-
cmp x0, #1
64-
b.lt .Lskip_pmu_\@ // Skip if no PMU present
62+
ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
63+
cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI
64+
ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
65+
b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF
6566
mrs x0, pmcr_el0 // Disable debug access traps
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ubfx x0, x0, #11, #5 // to EL2 and allow access to
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.Lskip_pmu_\@:
68-
csel x2, xzr, x0, lt // all PMU counters from EL1
69+
csel x2, xzr, x0, eq // all PMU counters from EL1
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/* Statistical profiling */
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ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4

arch/arm64/kernel/perf_callchain.c

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Original file line numberDiff line numberDiff line change
@@ -10,94 +10,12 @@
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1111
#include <asm/pointer_auth.h>
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13-
struct frame_tail {
14-
struct frame_tail __user *fp;
15-
unsigned long lr;
16-
} __attribute__((packed));
17-
18-
/*
19-
* Get the return address for a single stackframe and return a pointer to the
20-
* next frame tail.
21-
*/
22-
static struct frame_tail __user *
23-
user_backtrace(struct frame_tail __user *tail,
24-
struct perf_callchain_entry_ctx *entry)
25-
{
26-
struct frame_tail buftail;
27-
unsigned long err;
28-
unsigned long lr;
29-
30-
/* Also check accessibility of one struct frame_tail beyond */
31-
if (!access_ok(tail, sizeof(buftail)))
32-
return NULL;
33-
34-
pagefault_disable();
35-
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
36-
pagefault_enable();
37-
38-
if (err)
39-
return NULL;
40-
41-
lr = ptrauth_strip_user_insn_pac(buftail.lr);
42-
43-
perf_callchain_store(entry, lr);
44-
45-
/*
46-
* Frame pointers should strictly progress back up the stack
47-
* (towards higher addresses).
48-
*/
49-
if (tail >= buftail.fp)
50-
return NULL;
51-
52-
return buftail.fp;
53-
}
54-
55-
#ifdef CONFIG_COMPAT
56-
/*
57-
* The registers we're interested in are at the end of the variable
58-
* length saved register structure. The fp points at the end of this
59-
* structure so the address of this struct is:
60-
* (struct compat_frame_tail *)(xxx->fp)-1
61-
*
62-
* This code has been adapted from the ARM OProfile support.
63-
*/
64-
struct compat_frame_tail {
65-
compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
66-
u32 sp;
67-
u32 lr;
68-
} __attribute__((packed));
69-
70-
static struct compat_frame_tail __user *
71-
compat_user_backtrace(struct compat_frame_tail __user *tail,
72-
struct perf_callchain_entry_ctx *entry)
13+
static bool callchain_trace(void *data, unsigned long pc)
7314
{
74-
struct compat_frame_tail buftail;
75-
unsigned long err;
76-
77-
/* Also check accessibility of one struct frame_tail beyond */
78-
if (!access_ok(tail, sizeof(buftail)))
79-
return NULL;
80-
81-
pagefault_disable();
82-
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
83-
pagefault_enable();
84-
85-
if (err)
86-
return NULL;
87-
88-
perf_callchain_store(entry, buftail.lr);
89-
90-
/*
91-
* Frame pointers should strictly progress back up the stack
92-
* (towards higher addresses).
93-
*/
94-
if (tail + 1 >= (struct compat_frame_tail __user *)
95-
compat_ptr(buftail.fp))
96-
return NULL;
15+
struct perf_callchain_entry_ctx *entry = data;
9716

98-
return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
17+
return perf_callchain_store(entry, pc) == 0;
9918
}
100-
#endif /* CONFIG_COMPAT */
10119

10220
void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
10321
struct pt_regs *regs)
@@ -107,35 +25,7 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
10725
return;
10826
}
10927

110-
perf_callchain_store(entry, regs->pc);
111-
112-
if (!compat_user_mode(regs)) {
113-
/* AARCH64 mode */
114-
struct frame_tail __user *tail;
115-
116-
tail = (struct frame_tail __user *)regs->regs[29];
117-
118-
while (entry->nr < entry->max_stack &&
119-
tail && !((unsigned long)tail & 0x7))
120-
tail = user_backtrace(tail, entry);
121-
} else {
122-
#ifdef CONFIG_COMPAT
123-
/* AARCH32 compat mode */
124-
struct compat_frame_tail __user *tail;
125-
126-
tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
127-
128-
while ((entry->nr < entry->max_stack) &&
129-
tail && !((unsigned long)tail & 0x3))
130-
tail = compat_user_backtrace(tail, entry);
131-
#endif
132-
}
133-
}
134-
135-
static bool callchain_trace(void *data, unsigned long pc)
136-
{
137-
struct perf_callchain_entry_ctx *entry = data;
138-
return perf_callchain_store(entry, pc) == 0;
28+
arch_stack_walk_user(callchain_trace, entry, regs);
13929
}
14030

14131
void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,

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