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Merge tag 'iommu-updates-v6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/iommu/linux into iommufd.git
Merge with Joerg's tree for dependencies on the next patches. ====================================== IOMMU Updates for Linux v6.13: Including: - Core Updates: - Convert call-sites using iommu_domain_alloc() to more specific versions and remove function. - Introduce iommu_paging_domain_alloc_flags(). - Extend support for allocating PASID-capable domains to more drivers. - Remove iommu_present(). - Some smaller improvements. - New IOMMU driver for RISC-V. - Intel VT-d Updates: - Add domain_alloc_paging support. - Enable user space IOPFs in non-PASID and non-svm cases. - Small code refactoring and cleanups. - Add domain replacement support for pasid. - AMD-Vi Updates: - Adapt to iommu_paging_domain_alloc_flags() interface and alloc V2 page-tables by default. - Replace custom domain ID allocator with IDA allocator. - Add ops->release_domain() support. - Other improvements to device attach and domain allocation code paths. - ARM-SMMU Updates: - SMMUv2: - Return -EPROBE_DEFER for client devices probing before their SMMU. - Devicetree binding updates for Qualcomm MMU-500 implementations. - SMMUv3: - Minor fixes and cleanup for NVIDIA's virtual command queue driver. - IO-PGTable: - Fix indexing of concatenated PGDs and extend selftest coverage. - Remove unused block-splitting support. - S390 IOMMU: - Implement support for blocking domain. - Mediatek IOMMU: - Enable 35-bit physical address support for mt8186. - OMAP IOMMU driver: - Adapt to recent IOMMU core changes and unbreak driver. ====================================== Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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.mailmap

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@@ -73,6 +73,8 @@ Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>
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Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>
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André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>
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Andy Adamson <andros@citi.umich.edu>
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Andy Chiu <andybnac@gmail.com> <andy.chiu@sifive.com>
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Andy Chiu <andybnac@gmail.com> <taochiu@synology.com>
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Andy Shevchenko <andy@kernel.org> <andy@smile.org.ua>
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Andy Shevchenko <andy@kernel.org> <ext-andriy.shevchenko@nokia.com>
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Anilkumar Kolli <quic_akolli@quicinc.com> <akolli@codeaurora.org>
@@ -197,7 +199,8 @@ Elliot Berman <quic_eberman@quicinc.com> <eberman@codeaurora.org>
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Enric Balletbo i Serra <eballetbo@kernel.org> <enric.balletbo@collabora.com>
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Enric Balletbo i Serra <eballetbo@kernel.org> <eballetbo@iseebcn.com>
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Erik Kaneda <erik.kaneda@intel.com> <erik.schmauss@intel.com>
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Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
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Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
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Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
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Evgeniy Polyakov <johnpol@2ka.mipt.ru>
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Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> <ezequiel@collabora.com>
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Faith Ekstrand <faith.ekstrand@collabora.com> <jason@jlekstrand.net>
@@ -280,7 +283,7 @@ Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
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Jan Kuliga <jtkuliga.kdev@gmail.com> <jankul@alatek.krakow.pl>
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Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
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Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
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Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@tuni.fi>
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Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@parity.io>
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Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
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Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
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Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
@@ -304,6 +307,11 @@ Jens Axboe <axboe@kernel.dk> <axboe@fb.com>
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Jens Axboe <axboe@kernel.dk> <axboe@meta.com>
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Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
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Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
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Jesper Dangaard Brouer <hawk@kernel.org> <brouer@redhat.com>
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Jesper Dangaard Brouer <hawk@kernel.org> <hawk@comx.dk>
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Jesper Dangaard Brouer <hawk@kernel.org> <jbrouer@redhat.com>
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Jesper Dangaard Brouer <hawk@kernel.org> <jdb@comx.dk>
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Jesper Dangaard Brouer <hawk@kernel.org> <netoptimizer@brouer.com>
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Jessica Zhang <quic_jesszhan@quicinc.com> <jesszhan@codeaurora.org>
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Jilai Wang <quic_jilaiw@quicinc.com> <jilaiw@codeaurora.org>
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Jiri Kosina <jikos@kernel.org> <jikos@jikos.cz>
@@ -657,6 +665,7 @@ Tomeu Vizoso <tomeu@tomeuvizoso.net> <tomeu.vizoso@collabora.com>
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Thomas Graf <tgraf@suug.ch>
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Thomas Körper <socketcan@esd.eu> <thomas.koerper@esd.eu>
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Thomas Pedersen <twp@codeaurora.org>
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Thorsten Blum <thorsten.blum@linux.dev> <thorsten.blum@toblux.com>
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Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>
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Tingwei Zhang <quic_tingwei@quicinc.com> <tingwei@codeaurora.org>
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Tirupathi Reddy <quic_tirupath@quicinc.com> <tirupath@codeaurora.org>

CREDITS

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S: D-57250 Netphen
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S: Germany
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N: Florian Fainelli
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E: f.fainelli@gmail.com
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D: DSA
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N: Rik Faith
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E: faith@acm.org
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D: Future Domain TMC-16x0 SCSI driver (author)

Documentation/admin-guide/LSM/ipe.rst

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@@ -223,7 +223,10 @@ are signed through the PKCS#7 message format to enforce some level of
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authorization of the policies (prohibiting an attacker from gaining
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unconstrained root, and deploying an "allow all" policy). These
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policies must be signed by a certificate that chains to the
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``SYSTEM_TRUSTED_KEYRING``. With openssl, the policy can be signed by::
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``SYSTEM_TRUSTED_KEYRING``, or to the secondary and/or platform keyrings if
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``CONFIG_IPE_POLICY_SIG_SECONDARY_KEYRING`` and/or
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``CONFIG_IPE_POLICY_SIG_PLATFORM_KEYRING`` are enabled, respectively.
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With openssl, the policy can be signed by::
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openssl smime -sign \
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-in "$MY_POLICY" \
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policy. Two checks will always be performed on this policy: First, the
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``policy_names`` must match with the updated version and the existing
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version. Second the updated policy must have a policy version greater than
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or equal to the currently-running version. This is to prevent rollback attacks.
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the currently-running version. This is to prevent rollback attacks.
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The ``delete`` file is used to remove a policy that is no longer needed.
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This file is write-only and accepts a value of ``1`` to delete the policy.

Documentation/admin-guide/kernel-parameters.txt

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0: no polling (default)
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thp_anon= [KNL]
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Format: <size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>
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Format: <size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>
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state is one of "always", "madvise", "never" or "inherit".
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Control the default behavior of the system with respect
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to anonymous transparent hugepages.

Documentation/admin-guide/mm/transhuge.rst

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kernel command line.
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Alternatively, each supported anonymous THP size can be controlled by
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passing ``thp_anon=<size>,<size>[KMG]:<state>;<size>-<size>[KMG]:<state>``,
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passing ``thp_anon=<size>[KMG],<size>[KMG]:<state>;<size>[KMG]-<size>[KMG]:<state>``,
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where ``<size>`` is the THP size (must be a power of 2 of PAGE_SIZE and
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supported anonymous THP) and ``<state>`` is one of ``always``, ``madvise``,
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``never`` or ``inherit``.

Documentation/admin-guide/pm/cpufreq.rst

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``rate_limit_us``
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Minimum time (in microseconds) that has to pass between two consecutive
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runs of governor computations (default: 1000 times the scaling driver's
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transition latency).
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runs of governor computations (default: 1.5 times the scaling driver's
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transition latency or the maximum 2ms).
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The purpose of this tunable is to reduce the scheduler context overhead
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Typically, it is set to values of the order of 10000 (10 ms). Its
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default value is equal to the value of ``cpuinfo_transition_latency``
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for each policy this governor is attached to (but since the unit here
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is greater by 1000, this means that the time represented by
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``sampling_rate`` is 1000 times greater than the transition latency by
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default).
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Typically, it is set to values of the order of 2000 (2 ms). Its
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default value is to add a 50% breathing room
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to ``cpuinfo_transition_latency`` on each policy this governor is
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represented by it to be 1.5 times as high as the transition latency
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Documentation/core-api/protection-keys.rst

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@@ -12,7 +12,10 @@ Pkeys Userspace (PKU) is a feature which can be found on:
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* Intel client CPUs, Tiger Lake (11th Gen Core) and later
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* Future AMD CPUs
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* arm64 CPUs implementing the Permission Overlay Extension (FEAT_S1POE)
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x86_64
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======
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Pkeys work by dedicating 4 previously Reserved bits in each page table entry to
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arm64
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=====
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Pkeys use 3 bits in each page table entry, to encode a "protection key index",
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giving 8 possible keys.
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Protections for each key are defined with a per-CPU user-writable system
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register (POR_EL0). This is a 64-bit register encoding read, write and execute
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overlay permissions for each protection key index.
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Being a CPU register, POR_EL0 is inherently thread-local, potentially giving
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Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

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Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml

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Documentation/devicetree/bindings/firmware/arm,scmi.yaml

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