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konradybcioKAGA-KOKO
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irqchip/qcom-mpm: Support passing a slice of SRAM as reg space
The MPM hardware is accessible from the ARM CPUs through a shared memory region (RPM MSG RAM) which is also concurrently accessed by other kinds of cores on the system like modem, ADSP etc. Modeling this relation in a (somewhat) sane manner in the device tree requires to - either present the MPM as a child of said memory region, which makes little sense, as a mapped memory carveout is not a bus. - define nodes which bleed their register spaces into one another - or passing their slice of the MSG RAM through a property Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as register space for the MPM interrupt controller. The current way of using 'reg' is preserved for backwards compatibility reasons. [ tglx: Massaged changelog ] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v7-2-6ee2bfeaac2c@linaro.org
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drivers/irqchip/irq-qcom-mpm.c

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
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#include <linux/mailbox_client.h>
1515
#include <linux/module.h>
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#include <linux/of.h>
17+
#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
@@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
322323
struct device *dev = &pdev->dev;
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struct irq_domain *parent_domain;
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struct generic_pm_domain *genpd;
326+
struct device_node *msgram_np;
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struct qcom_mpm_priv *priv;
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unsigned int pin_cnt;
329+
struct resource res;
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int i, irq;
328331
int ret;
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@@ -374,9 +377,26 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
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375378
raw_spin_lock_init(&priv->lock);
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377-
priv->base = devm_platform_ioremap_resource(pdev, 0);
378-
if (IS_ERR(priv->base))
379-
return PTR_ERR(priv->base);
380+
/* If we have a handle to an RPM message ram partition, use it. */
381+
msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0);
382+
if (msgram_np) {
383+
ret = of_address_to_resource(msgram_np, 0, &res);
384+
if (ret) {
385+
of_node_put(msgram_np);
386+
return ret;
387+
}
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389+
/* Don't use devm_ioremap_resource, as we're accessing a shared region. */
390+
priv->base = devm_ioremap(dev, res.start, resource_size(&res));
391+
of_node_put(msgram_np);
392+
if (IS_ERR(priv->base))
393+
return PTR_ERR(priv->base);
394+
} else {
395+
/* Otherwise, fall back to simple MMIO. */
396+
priv->base = devm_platform_ioremap_resource(pdev, 0);
397+
if (IS_ERR(priv->base))
398+
return PTR_ERR(priv->base);
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}
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381401
for (i = 0; i < priv->reg_stride; i++) {
382402
qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);

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