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Merge patch series "RISC-V: ACPI: Enable CPPC based cpufreq support"
Sunil V L <sunilvl@ventanamicro.com> says: This series enables the support for "Collaborative Processor Performance Control (CPPC) on ACPI based RISC-V platforms. It depends on the encoding of CPPC registers as defined in RISC-V FFH spec [2]. CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to enable this, is available at [2]. [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf * b4-shazam-merge: RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver Link: https://lore.kernel.org/r/20240208034414.22579-1-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2 parents 01261e2 + 282b9df commit 028d1ae

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5 files changed

+188
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lines changed

‎arch/riscv/configs/defconfig

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@@ -44,6 +44,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
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CONFIG_CPUFREQ_DT=y
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CONFIG_ACPI_CPPC_CPUFREQ=m
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CONFIG_VIRTUALIZATION=y
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CONFIG_KVM=m
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CONFIG_ACPI=y

‎drivers/acpi/riscv/Makefile

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@@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += rhct.o
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obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
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obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o

‎drivers/acpi/riscv/cppc.c

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@@ -0,0 +1,157 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Implement CPPC FFH helper routines for RISC-V.
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*
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* Copyright (C) 2024 Ventana Micro Systems Inc.
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*/
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#include <acpi/cppc_acpi.h>
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#include <asm/csr.h>
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#include <asm/sbi.h>
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#define SBI_EXT_CPPC 0x43505043
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/* CPPC interfaces defined in SBI spec */
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#define SBI_CPPC_PROBE 0x0
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#define SBI_CPPC_READ 0x1
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#define SBI_CPPC_READ_HI 0x2
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#define SBI_CPPC_WRITE 0x3
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/* RISC-V FFH definitions from RISC-V FFH spec */
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#define FFH_CPPC_TYPE(r) (((r) & GENMASK_ULL(63, 60)) >> 60)
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#define FFH_CPPC_SBI_REG(r) ((r) & GENMASK(31, 0))
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#define FFH_CPPC_CSR_NUM(r) ((r) & GENMASK(11, 0))
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#define FFH_CPPC_SBI 0x1
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#define FFH_CPPC_CSR 0x2
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struct sbi_cppc_data {
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u64 val;
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u32 reg;
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struct sbiret ret;
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};
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static bool cppc_ext_present;
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static int __init sbi_cppc_init(void)
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{
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if (sbi_spec_version >= sbi_mk_version(2, 0) &&
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sbi_probe_extension(SBI_EXT_CPPC) > 0) {
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pr_info("SBI CPPC extension detected\n");
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cppc_ext_present = true;
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} else {
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pr_info("SBI CPPC extension NOT detected!!\n");
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cppc_ext_present = false;
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}
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return 0;
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}
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device_initcall(sbi_cppc_init);
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static void sbi_cppc_read(void *read_data)
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{
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struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
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data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_READ,
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data->reg, 0, 0, 0, 0, 0);
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}
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static void sbi_cppc_write(void *write_data)
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{
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struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
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data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_WRITE,
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data->reg, data->val, 0, 0, 0, 0);
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}
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static void cppc_ffh_csr_read(void *read_data)
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{
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struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
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switch (data->reg) {
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/* Support only TIME CSR for now */
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case CSR_TIME:
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data->ret.value = csr_read(CSR_TIME);
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data->ret.error = 0;
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break;
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default:
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data->ret.error = -EINVAL;
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break;
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}
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}
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static void cppc_ffh_csr_write(void *write_data)
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{
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struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
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data->ret.error = -EINVAL;
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}
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/*
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* Refer to drivers/acpi/cppc_acpi.c for the description of the functions
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* below.
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*/
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bool cpc_ffh_supported(void)
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{
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return true;
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}
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int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
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{
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struct sbi_cppc_data data;
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if (WARN_ON_ONCE(irqs_disabled()))
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return -EPERM;
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if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
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if (!cppc_ext_present)
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return -EINVAL;
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data.reg = FFH_CPPC_SBI_REG(reg->address);
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smp_call_function_single(cpu, sbi_cppc_read, &data, 1);
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*val = data.ret.value;
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return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
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} else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
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data.reg = FFH_CPPC_CSR_NUM(reg->address);
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smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1);
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*val = data.ret.value;
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return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
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}
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return -EINVAL;
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}
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int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
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{
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struct sbi_cppc_data data;
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if (WARN_ON_ONCE(irqs_disabled()))
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return -EPERM;
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if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
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if (!cppc_ext_present)
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return -EINVAL;
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data.reg = FFH_CPPC_SBI_REG(reg->address);
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data.val = val;
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smp_call_function_single(cpu, sbi_cppc_write, &data, 1);
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return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
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} else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
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data.reg = FFH_CPPC_CSR_NUM(reg->address);
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data.val = val;
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smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
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return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
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}
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return -EINVAL;
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}

‎drivers/cpufreq/Kconfig

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@@ -302,4 +302,33 @@ config QORIQ_CPUFREQ
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which are capable of changing the CPU's frequency dynamically.
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endif
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config ACPI_CPPC_CPUFREQ
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tristate "CPUFreq driver based on the ACPI CPPC spec"
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depends on ACPI_PROCESSOR
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depends on ARM || ARM64 || RISCV
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select ACPI_CPPC_LIB
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help
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This adds a CPUFreq driver which uses CPPC methods
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as described in the ACPIv5.1 spec. CPPC stands for
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Collaborative Processor Performance Controls. It
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is based on an abstract continuous scale of CPU
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performance values which allows the remote power
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processor to flexibly optimize for power and
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performance. CPPC relies on power management firmware
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support for its operation.
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If in doubt, say N.
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config ACPI_CPPC_CPUFREQ_FIE
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bool "Frequency Invariance support for CPPC cpufreq driver"
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depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
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depends on ARM || ARM64 || RISCV
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default y
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help
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This extends frequency invariance support in the CPPC cpufreq driver,
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by using CPPC delivered and reference performance counters.
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If in doubt, say N.
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endmenu

‎drivers/cpufreq/Kconfig.arm

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@@ -3,32 +3,6 @@
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# ARM CPU Frequency scaling drivers
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#
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config ACPI_CPPC_CPUFREQ
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tristate "CPUFreq driver based on the ACPI CPPC spec"
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depends on ACPI_PROCESSOR
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select ACPI_CPPC_LIB
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help
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This adds a CPUFreq driver which uses CPPC methods
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as described in the ACPIv5.1 spec. CPPC stands for
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Collaborative Processor Performance Controls. It
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is based on an abstract continuous scale of CPU
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performance values which allows the remote power
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processor to flexibly optimize for power and
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performance. CPPC relies on power management firmware
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support for its operation.
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If in doubt, say N.
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config ACPI_CPPC_CPUFREQ_FIE
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bool "Frequency Invariance support for CPPC cpufreq driver"
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depends on ACPI_CPPC_CPUFREQ && GENERIC_ARCH_TOPOLOGY
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default y
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help
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This extends frequency invariance support in the CPPC cpufreq driver,
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by using CPPC delivered and reference performance counters.
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If in doubt, say N.
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config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
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tristate "Allwinner nvmem based SUN50I CPUFreq driver"
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depends on ARCH_SUNXI

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