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[AArch64] Reuse larger DUPLANE if available
As combining DUP, try to reuse larger DUPLANELANE. Differential Revision: https://reviews.llvm.org/D155592
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4 files changed

+175
-35
lines changed

4 files changed

+175
-35
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22107,15 +22107,19 @@ static SDValue performDUPCombine(SDNode *N,
2210722107
// 128bit vector version.
2210822108
if (VT.is64BitVector() && DCI.isAfterLegalizeDAG()) {
2210922109
EVT LVT = VT.getDoubleNumVectorElementsVT(*DCI.DAG.getContext());
22110-
if (SDNode *LN = DCI.DAG.getNodeIfExists(
22111-
N->getOpcode(), DCI.DAG.getVTList(LVT), {N->getOperand(0)})) {
22110+
SmallVector<SDValue> Ops(N->ops());
22111+
if (SDNode *LN = DCI.DAG.getNodeIfExists(N->getOpcode(),
22112+
DCI.DAG.getVTList(LVT), Ops)) {
2211222113
SDLoc DL(N);
2211322114
return DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SDValue(LN, 0),
2211422115
DCI.DAG.getConstant(0, DL, MVT::i64));
2211522116
}
2211622117
}
2211722118

22118-
return performPostLD1Combine(N, DCI, false);
22119+
if (N->getOpcode() == AArch64ISD::DUP)
22120+
return performPostLD1Combine(N, DCI, false);
22121+
22122+
return SDValue();
2211922123
}
2212022124

2212122125
/// Get rid of unnecessary NVCASTs (that don't change the type).
@@ -23043,6 +23047,10 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2304323047
case AArch64ISD::CSEL:
2304423048
return performCSELCombine(N, DCI, DAG);
2304523049
case AArch64ISD::DUP:
23050+
case AArch64ISD::DUPLANE8:
23051+
case AArch64ISD::DUPLANE16:
23052+
case AArch64ISD::DUPLANE32:
23053+
case AArch64ISD::DUPLANE64:
2304623054
return performDUPCombine(N, DCI);
2304723055
case AArch64ISD::DUPLANE128:
2304823056
return performDupLane128Combine(N, DAG);

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 39 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,23 @@ def extract_high_dup_v8i16 :
138138
def extract_high_dup_v4i32 :
139139
BinOpFrag<(extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 2))>;
140140

141+
def dup_v8i16 :
142+
PatFrags<(ops node:$LHS, node:$RHS),
143+
[(v4i16 (extract_subvector (v8i16 (AArch64duplane16 (v8i16 node:$LHS), node:$RHS)), (i64 0))),
144+
(v4i16 (AArch64duplane16 (v8i16 node:$LHS), node:$RHS))]>;
145+
def dup_v4i32 :
146+
PatFrags<(ops node:$LHS, node:$RHS),
147+
[(v2i32 (extract_subvector (v4i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS)), (i64 0))),
148+
(v2i32 (AArch64duplane32 (v4i32 node:$LHS), node:$RHS))]>;
149+
def dup_v8f16 :
150+
PatFrags<(ops node:$LHS, node:$RHS),
151+
[(v4f16 (extract_subvector (v8f16 (AArch64duplane16 (v8f16 node:$LHS), node:$RHS)), (i64 0))),
152+
(v4f16 (AArch64duplane16 (v8f16 node:$LHS), node:$RHS))]>;
153+
def dup_v4f32 :
154+
PatFrags<(ops node:$LHS, node:$RHS),
155+
[(v2f32 (extract_subvector (v4f32 (AArch64duplane32 (v4f32 node:$LHS), node:$RHS)), (i64 0))),
156+
(v2f32 (AArch64duplane32 (v4f32 node:$LHS), node:$RHS))]>;
157+
141158
//===----------------------------------------------------------------------===//
142159
// Asm Operand Classes.
143160
//
@@ -8443,7 +8460,7 @@ multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
84438460
asm, ".4h", ".4h", ".4h", ".h",
84448461
[(set (v4f16 V64:$Rd),
84458462
(OpNode (v4f16 V64:$Rn),
8446-
(v4f16 (AArch64duplane16 (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
8463+
(dup_v8f16 (v8f16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
84478464
bits<3> idx;
84488465
let Inst{11} = idx{2};
84498466
let Inst{21} = idx{1};
@@ -8470,7 +8487,7 @@ multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
84708487
asm, ".2s", ".2s", ".2s", ".s",
84718488
[(set (v2f32 V64:$Rd),
84728489
(OpNode (v2f32 V64:$Rn),
8473-
(v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
8490+
(dup_v4f32 (v4f32 V128:$Rm), VectorIndexS:$idx)))]> {
84748491
bits<2> idx;
84758492
let Inst{11} = idx{1};
84768493
let Inst{21} = idx{0};
@@ -8781,7 +8798,7 @@ multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
87818798
asm, ".4h", ".4h", ".4h", ".h",
87828799
[(set (v4i16 V64:$Rd),
87838800
(OpNode (v4i16 V64:$Rn),
8784-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
8801+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
87858802
bits<3> idx;
87868803
let Inst{11} = idx{2};
87878804
let Inst{21} = idx{1};
@@ -8807,7 +8824,7 @@ multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
88078824
asm, ".2s", ".2s", ".2s", ".s",
88088825
[(set (v2i32 V64:$Rd),
88098826
(OpNode (v2i32 V64:$Rn),
8810-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
8827+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
88118828
bits<2> idx;
88128829
let Inst{11} = idx{1};
88138830
let Inst{21} = idx{0};
@@ -8855,7 +8872,7 @@ multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
88558872
asm, ".4h", ".4h", ".4h", ".h",
88568873
[(set (v4i16 V64:$Rd),
88578874
(OpNode (v4i16 V64:$Rn),
8858-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
8875+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
88598876
bits<3> idx;
88608877
let Inst{11} = idx{2};
88618878
let Inst{21} = idx{1};
@@ -8881,7 +8898,7 @@ multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
88818898
asm, ".2s", ".2s", ".2s", ".s",
88828899
[(set (v2i32 V64:$Rd),
88838900
(OpNode (v2i32 V64:$Rn),
8884-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
8901+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
88858902
bits<2> idx;
88868903
let Inst{11} = idx{1};
88878904
let Inst{21} = idx{0};
@@ -8907,7 +8924,7 @@ multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
89078924
asm, ".4h", ".4h", ".4h", ".h",
89088925
[(set (v4i16 V64:$dst),
89098926
(OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
8910-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
8927+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
89118928
bits<3> idx;
89128929
let Inst{11} = idx{2};
89138930
let Inst{21} = idx{1};
@@ -8933,7 +8950,7 @@ multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
89338950
asm, ".2s", ".2s", ".2s", ".s",
89348951
[(set (v2i32 V64:$dst),
89358952
(OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8936-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
8953+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
89378954
bits<2> idx;
89388955
let Inst{11} = idx{1};
89398956
let Inst{21} = idx{0};
@@ -8960,7 +8977,7 @@ multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
89608977
asm, ".4s", ".4s", ".4h", ".h",
89618978
[(set (v4i32 V128:$Rd),
89628979
(OpNode (v4i16 V64:$Rn),
8963-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
8980+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
89648981
bits<3> idx;
89658982
let Inst{11} = idx{2};
89668983
let Inst{21} = idx{1};
@@ -8987,7 +9004,7 @@ multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
89879004
asm, ".2d", ".2d", ".2s", ".s",
89889005
[(set (v2i64 V128:$Rd),
89899006
(OpNode (v2i32 V64:$Rn),
8990-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9007+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
89919008
bits<2> idx;
89929009
let Inst{11} = idx{1};
89939010
let Inst{21} = idx{0};
@@ -9033,8 +9050,8 @@ multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
90339050
(Accum (v4i32 V128:$Rd),
90349051
(v4i32 (int_aarch64_neon_sqdmull
90359052
(v4i16 V64:$Rn),
9036-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
9037-
VectorIndexH:$idx))))))]> {
9053+
(dup_v8i16 (v8i16 V128_lo:$Rm),
9054+
VectorIndexH:$idx)))))]> {
90389055
bits<3> idx;
90399056
let Inst{11} = idx{2};
90409057
let Inst{21} = idx{1};
@@ -9064,8 +9081,7 @@ multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
90649081
(Accum (v2i64 V128:$Rd),
90659082
(v2i64 (int_aarch64_neon_sqdmull
90669083
(v2i32 V64:$Rn),
9067-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
9068-
VectorIndexS:$idx))))))]> {
9084+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))))]> {
90699085
bits<2> idx;
90709086
let Inst{11} = idx{1};
90719087
let Inst{21} = idx{0};
@@ -9110,9 +9126,8 @@ multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
91109126
(i32 (vector_extract
91119127
(v4i32 (int_aarch64_neon_sqdmull
91129128
(v4i16 V64:$Rn),
9113-
(v4i16 (AArch64duplane16
9114-
(v8i16 V128_lo:$Rm),
9115-
VectorIndexH:$idx)))),
9129+
(dup_v8i16 (v8i16 V128_lo:$Rm),
9130+
VectorIndexH:$idx))),
91169131
(i64 0))))),
91179132
(!cast<Instruction>(NAME # v1i32_indexed)
91189133
FPR32Op:$Rd,
@@ -9145,7 +9160,7 @@ multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
91459160
asm, ".4s", ".4s", ".4h", ".h",
91469161
[(set (v4i32 V128:$Rd),
91479162
(OpNode (v4i16 V64:$Rn),
9148-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
9163+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
91499164
bits<3> idx;
91509165
let Inst{11} = idx{2};
91519166
let Inst{21} = idx{1};
@@ -9172,7 +9187,7 @@ multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
91729187
asm, ".2d", ".2d", ".2s", ".s",
91739188
[(set (v2i64 V128:$Rd),
91749189
(OpNode (v2i32 V64:$Rn),
9175-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9190+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
91769191
bits<2> idx;
91779192
let Inst{11} = idx{1};
91789193
let Inst{21} = idx{0};
@@ -9201,7 +9216,7 @@ multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
92019216
asm, ".4s", ".4s", ".4h", ".h",
92029217
[(set (v4i32 V128:$dst),
92039218
(OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
9204-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
9219+
(dup_v8i16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))]> {
92059220
bits<3> idx;
92069221
let Inst{11} = idx{2};
92079222
let Inst{21} = idx{1};
@@ -9228,7 +9243,7 @@ multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
92289243
asm, ".2d", ".2d", ".2s", ".s",
92299244
[(set (v2i64 V128:$dst),
92309245
(OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
9231-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
9246+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx)))]> {
92329247
bits<2> idx;
92339248
let Inst{11} = idx{1};
92349249
let Inst{21} = idx{0};
@@ -10850,8 +10865,8 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
1085010865
asm, ".4h", ".4h", ".4h", ".h",
1085110866
[(set (v4i16 V64:$dst),
1085210867
(v4i16 (op (v4i16 V64:$Rd), (v4i16 V64:$Rn),
10853-
(v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
10854-
VectorIndexH:$idx)))))]> {
10868+
(dup_v8i16 (v8i16 V128_lo:$Rm),
10869+
VectorIndexH:$idx))))]> {
1085510870
bits<3> idx;
1085610871
let Inst{11} = idx{2};
1085710872
let Inst{21} = idx{1};
@@ -10876,8 +10891,7 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
1087610891
asm, ".2s", ".2s", ".2s", ".s",
1087710892
[(set (v2i32 V64:$dst),
1087810893
(v2i32 (op (v2i32 V64:$Rd), (v2i32 V64:$Rn),
10879-
(v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
10880-
VectorIndexS:$idx)))))]> {
10894+
(dup_v4i32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
1088110895
bits<2> idx;
1088210896
let Inst{11} = idx{1};
1088310897
let Inst{21} = idx{0};

‎llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -657,20 +657,19 @@ exit:
657657
define void @sink_v16s16_8(i32 *%p, i32 *%d, i64 %n, <16 x i8> %a) {
658658
; CHECK-LABEL: sink_v16s16_8:
659659
; CHECK: // %bb.0: // %entry
660-
; CHECK-NEXT: dup v1.8b, v0.b[10]
661660
; CHECK-NEXT: mov x8, xzr
662661
; CHECK-NEXT: dup v0.16b, v0.b[10]
663662
; CHECK-NEXT: .LBB9_1: // %loop
664663
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
665-
; CHECK-NEXT: ldr q2, [x0]
664+
; CHECK-NEXT: ldr q1, [x0]
666665
; CHECK-NEXT: add x8, x8, #8
667666
; CHECK-NEXT: subs x2, x2, #8
668-
; CHECK-NEXT: smull2 v3.8h, v2.16b, v0.16b
669-
; CHECK-NEXT: smull v2.8h, v2.8b, v1.8b
670-
; CHECK-NEXT: cmlt v3.8h, v3.8h, #0
667+
; CHECK-NEXT: smull2 v2.8h, v1.16b, v0.16b
668+
; CHECK-NEXT: smull v1.8h, v1.8b, v0.8b
671669
; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
672-
; CHECK-NEXT: uzp1 v2.16b, v2.16b, v3.16b
673-
; CHECK-NEXT: str q2, [x0], #32
670+
; CHECK-NEXT: cmlt v1.8h, v1.8h, #0
671+
; CHECK-NEXT: uzp1 v1.16b, v1.16b, v2.16b
672+
; CHECK-NEXT: str q1, [x0], #32
674673
; CHECK-NEXT: b.ne .LBB9_1
675674
; CHECK-NEXT: // %bb.2: // %exit
676675
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2+
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+fullfp16 < %s | FileCheck %s
3+
4+
define <8 x half> @sel.v8f16.fmul(ptr %p, ptr %q, <8 x half> %a, <8 x half> %b, <4 x half> %c) {
5+
; CHECK-LABEL: sel.v8f16.fmul:
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: fmul v1.8h, v1.8h, v0.h[0]
8+
; CHECK-NEXT: fmul v2.4h, v2.4h, v0.h[0]
9+
; CHECK-NEXT: mov v0.16b, v1.16b
10+
; CHECK-NEXT: str d2, [x0]
11+
; CHECK-NEXT: ret
12+
%splat = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer
13+
%splat2 = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> zeroinitializer
14+
15+
%r = fmul <8 x half> %b, %splat
16+
%r2 = fmul <4 x half> %c, %splat2
17+
store <4 x half> %r2, ptr %p
18+
ret <8 x half> %r
19+
}
20+
21+
define <4 x float> @sel.v4f32.fmul(ptr %p, ptr %q, <4 x float> %a, <4 x float> %b, <2 x float> %c) {
22+
; CHECK-LABEL: sel.v4f32.fmul:
23+
; CHECK: // %bb.0:
24+
; CHECK-NEXT: fmul v1.4s, v1.4s, v0.s[0]
25+
; CHECK-NEXT: fmul v2.2s, v2.2s, v0.s[0]
26+
; CHECK-NEXT: mov v0.16b, v1.16b
27+
; CHECK-NEXT: str d2, [x0]
28+
; CHECK-NEXT: ret
29+
%splat = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> zeroinitializer
30+
%splat2 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> zeroinitializer
31+
32+
%r = fmul <4 x float> %b, %splat
33+
%r2 = fmul <2 x float> %c, %splat2
34+
store <2 x float> %r2, ptr %p
35+
ret <4 x float> %r
36+
}
37+
38+
define <8 x i16> @sel.v8i16.mul(ptr %p, ptr %q, <8 x i16> %a, <8 x i16> %b, <4 x i16> %c) {
39+
; CHECK-LABEL: sel.v8i16.mul:
40+
; CHECK: // %bb.0:
41+
; CHECK-NEXT: mul v1.8h, v1.8h, v0.h[0]
42+
; CHECK-NEXT: mul v2.4h, v2.4h, v0.h[0]
43+
; CHECK-NEXT: mov v0.16b, v1.16b
44+
; CHECK-NEXT: str d2, [x0]
45+
; CHECK-NEXT: ret
46+
%splat = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> zeroinitializer
47+
%splat2 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> zeroinitializer
48+
49+
%r = mul <8 x i16> %b, %splat
50+
%r2 = mul <4 x i16> %c, %splat2
51+
store <4 x i16> %r2, ptr %p
52+
ret <8 x i16> %r
53+
}
54+
55+
define <4 x i32> @sel.v4i32.mul(ptr %p, ptr %q, <4 x i32> %a, <4 x i32> %b, <2 x i32> %c) {
56+
; CHECK-LABEL: sel.v4i32.mul:
57+
; CHECK: // %bb.0:
58+
; CHECK-NEXT: mul v1.4s, v1.4s, v0.s[0]
59+
; CHECK-NEXT: mul v2.2s, v2.2s, v0.s[0]
60+
; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: str d2, [x0]
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; CHECK-NEXT: ret
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%splat = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> zeroinitializer
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%splat2 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> zeroinitializer
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%r = mul <4 x i32> %b, %splat
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%r2 = mul <2 x i32> %c, %splat2
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store <2 x i32> %r2, ptr %p
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ret <4 x i32> %r
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}
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define <4 x i64> @sel.v4i32.smull(<4 x i32> %a, <4 x i32> %b, <2 x i32> %c) {
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; CHECK-LABEL: sel.v4i32.smull:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smull2 v2.2d, v1.4s, v0.s[0]
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; CHECK-NEXT: smull v0.2d, v1.2s, v0.s[0]
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; CHECK-NEXT: mov v1.16b, v2.16b
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; CHECK-NEXT: ret
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%ext = sext <4 x i32> %a to <4 x i64>
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%splat = shufflevector <4 x i64> %ext, <4 x i64> poison, <4 x i32> zeroinitializer
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%d = sext <4 x i32> %b to <4 x i64>
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%r = mul <4 x i64> %d, %splat
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ret <4 x i64> %r
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}
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define <4 x i64> @sel.v4i32.umull(<4 x i32> %a, <4 x i32> %b, <2 x i32> %c) {
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; CHECK-LABEL: sel.v4i32.umull:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umull2 v2.2d, v1.4s, v0.s[0]
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; CHECK-NEXT: umull v0.2d, v1.2s, v0.s[0]
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; CHECK-NEXT: mov v1.16b, v2.16b
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; CHECK-NEXT: ret
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%ext = zext <4 x i32> %a to <4 x i64>
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%splat = shufflevector <4 x i64> %ext, <4 x i64> poison, <4 x i32> zeroinitializer
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%d = zext <4 x i32> %b to <4 x i64>
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%r = mul <4 x i64> %d, %splat
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ret <4 x i64> %r
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}
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define <4 x i32> @sel.v4i32.sqdmull(<8 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: sel.v4i32.sqdmull:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: sqdmull v2.4s, v0.4h, v1.h[0]
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; CHECK-NEXT: sqdmlal2 v2.4s, v0.8h, v1.h[0]
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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entry:
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%c = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%d = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer
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%e = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %c, <4 x i16> %d)
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%f = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%g = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %f, <4 x i16> %d)
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%h = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %e, <4 x i32> %g)
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ret <4 x i32> %h
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}
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declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
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declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)

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