Skip to content

Commit 4dad491

Browse files
arsenmarsenm
committed
CodeGen: Use Register
1 parent 0368c1d commit 4dad491

14 files changed

+69
-70
lines changed

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -397,9 +397,9 @@ class MachineFunction {
397397
/// For now we support only cases when argument is transferred through one
398398
/// register.
399399
struct ArgRegPair {
400-
unsigned Reg;
400+
Register Reg;
401401
uint16_t ArgNo;
402-
ArgRegPair(unsigned R, unsigned Arg) : Reg(R), ArgNo(Arg) {
402+
ArgRegPair(Register R, unsigned Arg) : Reg(R), ArgNo(Arg) {
403403
assert(Arg < (1 << 16) && "Arg out of range");
404404
}
405405
};
@@ -690,7 +690,7 @@ class MachineFunction {
690690

691691
/// addLiveIn - Add the specified physical register as a live-in value and
692692
/// create a corresponding virtual register for it.
693-
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
693+
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC);
694694

695695
//===--------------------------------------------------------------------===//
696696
// BasicBlock accessor functions.

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -658,10 +658,10 @@ void MachineFunction::viewCFGOnly() const
658658

659659
/// Add the specified physical register as a live-in value and
660660
/// create a corresponding virtual register for it.
661-
unsigned MachineFunction::addLiveIn(unsigned PReg,
661+
Register MachineFunction::addLiveIn(MCRegister PReg,
662662
const TargetRegisterClass *RC) {
663663
MachineRegisterInfo &MRI = getRegInfo();
664-
unsigned VReg = MRI.getLiveInVirtReg(PReg);
664+
Register VReg = MRI.getLiveInVirtReg(PReg);
665665
if (VReg) {
666666
const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
667667
(void)VRegRC;

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -444,19 +444,19 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
444444
SIMachineFunctionInfo &Info) {
445445
// FIXME: How should these inputs interact with inreg / custom SGPR inputs?
446446
if (Info.hasPrivateSegmentBuffer()) {
447-
unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
447+
Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
448448
MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
449449
CCInfo.AllocateReg(PrivateSegmentBufferReg);
450450
}
451451

452452
if (Info.hasDispatchPtr()) {
453-
unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
453+
Register DispatchPtrReg = Info.addDispatchPtr(TRI);
454454
MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
455455
CCInfo.AllocateReg(DispatchPtrReg);
456456
}
457457

458458
if (Info.hasQueuePtr()) {
459-
unsigned QueuePtrReg = Info.addQueuePtr(TRI);
459+
Register QueuePtrReg = Info.addQueuePtr(TRI);
460460
MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
461461
CCInfo.AllocateReg(QueuePtrReg);
462462
}
@@ -473,13 +473,13 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
473473
}
474474

475475
if (Info.hasDispatchID()) {
476-
unsigned DispatchIDReg = Info.addDispatchID(TRI);
476+
Register DispatchIDReg = Info.addDispatchID(TRI);
477477
MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
478478
CCInfo.AllocateReg(DispatchIDReg);
479479
}
480480

481481
if (Info.hasFlatScratchInit()) {
482-
unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
482+
Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
483483
MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
484484
CCInfo.AllocateReg(FlatScratchInitReg);
485485
}

‎llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ using namespace llvm;
1212

1313
void LanaiMachineFunctionInfo::anchor() {}
1414

15-
unsigned LanaiMachineFunctionInfo::getGlobalBaseReg() {
15+
Register LanaiMachineFunctionInfo::getGlobalBaseReg() {
1616
// Return if it has already been initialized.
1717
if (GlobalBaseReg)
1818
return GlobalBaseReg;

‎llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,24 +29,24 @@ class LanaiMachineFunctionInfo : public MachineFunctionInfo {
2929
// SRetReturnReg - Lanai ABI require that sret lowering includes
3030
// returning the value of the returned struct in a register. This field
3131
// holds the virtual register into which the sret argument is passed.
32-
unsigned SRetReturnReg;
32+
Register SRetReturnReg;
3333

3434
// GlobalBaseReg - keeps track of the virtual register initialized for
3535
// use as the global base register. This is used for PIC in some PIC
3636
// relocation models.
37-
unsigned GlobalBaseReg;
37+
Register GlobalBaseReg;
3838

3939
// VarArgsFrameIndex - FrameIndex for start of varargs area.
4040
int VarArgsFrameIndex;
4141

4242
public:
4343
explicit LanaiMachineFunctionInfo(MachineFunction &MF)
44-
: MF(MF), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0) {}
44+
: MF(MF), VarArgsFrameIndex(0) {}
4545

46-
unsigned getSRetReturnReg() const { return SRetReturnReg; }
47-
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
46+
Register getSRetReturnReg() const { return SRetReturnReg; }
47+
void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
4848

49-
unsigned getGlobalBaseReg();
49+
Register getGlobalBaseReg();
5050

5151
int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
5252
void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }

‎llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ class MSP430MachineFunctionInfo : public MachineFunctionInfo {
3535
/// SRetReturnReg - Some subtargets require that sret lowering includes
3636
/// returning the value of the returned struct in a register. This field
3737
/// holds the virtual register into which the sret argument is passed.
38-
unsigned SRetReturnReg = 0;
38+
Register SRetReturnReg;
3939

4040
public:
4141
MSP430MachineFunctionInfo() = default;
@@ -46,8 +46,8 @@ class MSP430MachineFunctionInfo : public MachineFunctionInfo {
4646
unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
4747
void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
4848

49-
unsigned getSRetReturnReg() const { return SRetReturnReg; }
50-
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
49+
Register getSRetReturnReg() const { return SRetReturnReg; }
50+
void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
5151

5252
int getRAIndex() const { return ReturnAddrIndex; }
5353
void setRAIndex(int Index) { ReturnAddrIndex = Index; }

‎llvm/lib/Target/Mips/MipsMachineFunction.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -68,14 +68,13 @@ void MipsFunctionInfo::initGlobalBaseReg() {
6868
MachineRegisterInfo &RegInfo = MF.getRegInfo();
6969
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
7070
DebugLoc DL;
71-
unsigned V0, V1;
7271
const TargetRegisterClass *RC;
7372
const MipsABIInfo &ABI =
7473
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
7574
RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
7675

77-
V0 = RegInfo.createVirtualRegister(RC);
78-
V1 = RegInfo.createVirtualRegister(RC);
76+
Register V0 = RegInfo.createVirtualRegister(RC);
77+
Register V1 = RegInfo.createVirtualRegister(RC);
7978

8079
if (ABI.IsN64()) {
8180
MF.getRegInfo().addLiveIn(Mips::T9_64);

‎llvm/lib/Target/Mips/MipsMachineFunction.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ class MipsFunctionInfo : public MachineFunctionInfo {
6666
bool isISR() const { return IsISR; }
6767
void setISR() { IsISR = true; }
6868
void createISRRegFI();
69-
int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; }
69+
int getISRRegFI(Register Reg) const { return ISRDataRegFI[Reg]; }
7070
bool isISRRegFI(int FI) const;
7171

7272
/// Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object
@@ -89,12 +89,12 @@ class MipsFunctionInfo : public MachineFunctionInfo {
8989
/// SRetReturnReg - Some subtargets require that sret lowering includes
9090
/// returning the value of the returned struct in a register. This field
9191
/// holds the virtual register into which the sret argument is passed.
92-
unsigned SRetReturnReg = 0;
92+
Register SRetReturnReg;
9393

9494
/// GlobalBaseReg - keeps track of the virtual register initialized for
9595
/// use as the global base register. This is used for PIC in some PIC
9696
/// relocation models.
97-
unsigned GlobalBaseReg = 0;
97+
Register GlobalBaseReg;
9898

9999
/// VarArgsFrameIndex - FrameIndex for start of varargs area.
100100
int VarArgsFrameIndex = 0;

‎llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -571,11 +571,11 @@ bool
571571
PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
572572
bool UseAtEnd,
573573
bool TwoUniqueRegsRequired,
574-
unsigned *SR1,
575-
unsigned *SR2) const {
574+
Register *SR1,
575+
Register *SR2) const {
576576
RegScavenger RS;
577-
unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
578-
unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
577+
Register R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
578+
Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
579579

580580
// Set the defaults for the two scratch registers.
581581
if (SR1)
@@ -642,7 +642,7 @@ PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
642642
if (SecondScratchReg != -1)
643643
*SR2 = SecondScratchReg;
644644
else
645-
*SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
645+
*SR2 = TwoUniqueRegsRequired ? Register() : *SR1;
646646
}
647647

648648
// Now that we've done our best to provide both registers, double check
@@ -779,20 +779,20 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
779779
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
780780
bool MustSaveLR = FI->mustSaveLR();
781781
bool MustSaveTOC = FI->mustSaveTOC();
782-
const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
782+
const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();
783783
bool MustSaveCR = !MustSaveCRs.empty();
784784
// Do we have a frame pointer and/or base pointer for this function?
785785
bool HasFP = hasFP(MF);
786786
bool HasBP = RegInfo->hasBasePointer(MF);
787787
bool HasRedZone = isPPC64 || !isSVR4ABI;
788788

789-
unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
789+
Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
790790
Register BPReg = RegInfo->getBaseRegister(MF);
791-
unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
792-
unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
793-
unsigned TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
794-
unsigned ScratchReg = 0;
795-
unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
791+
Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
792+
Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
793+
Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
794+
Register ScratchReg;
795+
Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
796796
// ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
797797
const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
798798
: PPC::MFLR );
@@ -1339,18 +1339,18 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
13391339
// Check if the link register (LR) has been saved.
13401340
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
13411341
bool MustSaveLR = FI->mustSaveLR();
1342-
const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1342+
const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();
13431343
bool MustSaveCR = !MustSaveCRs.empty();
13441344
// Do we have a frame pointer and/or base pointer for this function?
13451345
bool HasFP = hasFP(MF);
13461346
bool HasBP = RegInfo->hasBasePointer(MF);
13471347
bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
13481348

1349-
unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1349+
Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
13501350
Register BPReg = RegInfo->getBaseRegister(MF);
1351-
unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1352-
unsigned ScratchReg = 0;
1353-
unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1351+
Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1352+
Register ScratchReg;
1353+
Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
13541354
const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
13551355
: PPC::MTLR );
13561356
const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD

‎llvm/lib/Target/PowerPC/PPCFrameLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,8 @@ class PPCFrameLowering: public TargetFrameLowering {
6161
bool findScratchRegister(MachineBasicBlock *MBB,
6262
bool UseAtEnd,
6363
bool TwoUniqueRegsRequired = false,
64-
unsigned *SR1 = nullptr,
65-
unsigned *SR2 = nullptr) const;
64+
Register *SR1 = nullptr,
65+
Register *SR2 = nullptr) const;
6666
bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
6767

6868
/**

0 commit comments

Comments
 (0)