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[Bitcode] Convert tests to opaque pointers (NFC)
1 parent 9dbf362 commit 45067d1

6 files changed

+81
-84
lines changed

‎llvm/test/Bitcode/function-nonzero-address-spaces-types.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,20 +4,20 @@
44

55
; We should get a sensible error for a non-program address call:
66
; RUN: not llvm-as -data-layout "P39" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS39
7-
; ERR-AS39: error: '%0' defined with type 'i16 (i16) addrspace(40)*' but expected 'i16 (i16) addrspace(39)*'
7+
; ERR-AS39: error: '%0' defined with type 'ptr addrspace(40)' but expected 'ptr addrspace(39)'
88

99
; And also if we don't set a custom program address space:
1010
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS0
11-
; ERR-AS0: error: '%0' defined with type 'i16 (i16) addrspace(40)*' but expected 'i16 (i16)*'
11+
; ERR-AS0: error: '%0' defined with type 'ptr addrspace(40)' but expected 'ptr'
1212

1313
%fun1 = type i16 (i16)
14-
%funptr1 = type %fun1 addrspace(40)*
14+
%funptr1 = type ptr addrspace(40)
1515

1616
@fun_ptr = global %funptr1 @fun
1717

1818
define i16 @fun(i16 %arg) addrspace(40) {
1919
entry:
20-
%0 = load %funptr1, %funptr1* @fun_ptr
20+
%0 = load %funptr1, ptr @fun_ptr
2121
%result = call i16 %0(i16 %arg)
2222
ret i16 %result
2323
}

‎llvm/test/Bitcode/function-nonzero-address-spaces.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4,26 +4,26 @@
44

55
; We should get a sensible error for a non-program address call:
66
; RUN: not llvm-as -data-layout "P39" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS39
7-
; ERR-AS39: error: '%fnptr' defined with type 'void (i16) addrspace(40)*' but expected 'void (i16) addrspace(39)*'
7+
; ERR-AS39: error: '%fnptr' defined with type 'ptr addrspace(40)' but expected 'ptr addrspace(39)'
88

99
; And also if we don't set a custom program address space:
1010
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS0
11-
; ERR-AS0: error: '%fnptr' defined with type 'void (i16) addrspace(40)*' but expected 'void (i16)*'
11+
; ERR-AS0: error: '%fnptr' defined with type 'ptr addrspace(40)' but expected 'ptr'
1212

13-
define void @f_named(i16 %n, void (i16) addrspace(40)* %f) addrspace(40) {
13+
define void @f_named(i16 %n, ptr addrspace(40) %f) addrspace(40) {
1414
entry:
15-
%f.addr = alloca void (i16) addrspace(40)*, align 1
16-
store void (i16) addrspace(40)* %f, void (i16) addrspace(40)** %f.addr
17-
%fnptr = load void (i16) addrspace(40)*, void (i16) addrspace(40)** %f.addr
15+
%f.addr = alloca ptr addrspace(40), align 1
16+
store ptr addrspace(40) %f, ptr %f.addr
17+
%fnptr = load ptr addrspace(40), ptr %f.addr
1818
call void %fnptr(i16 8)
1919
ret void
2020
}
2121

22-
define void @f_numbered(i16 %n, void (i16) addrspace(40)* %f) addrspace(40){
22+
define void @f_numbered(i16 %n, ptr addrspace(40) %f) addrspace(40){
2323
entry:
24-
%f.addr = alloca void (i16) addrspace(40)*, align 1
25-
store void (i16) addrspace(40)* %f, void (i16) addrspace(40)** %f.addr
26-
%0 = load void (i16) addrspace(40)*, void (i16) addrspace(40)** %f.addr
24+
%f.addr = alloca ptr addrspace(40), align 1
25+
store ptr addrspace(40) %f, ptr %f.addr
26+
%0 = load ptr addrspace(40), ptr %f.addr
2727
call void %0(i16 8)
2828
ret void
2929
}

‎llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
; CHECK-NEXT: <VERSION
88
; CHECK-NEXT: <FLAGS
99
; "op7" is a call to "callee" function.
10-
; CHECK-NEXT: <PERMODULE {{.*}} op9=3 op10=[[ALIASID:[0-9]+]]/>
10+
; CHECK-NEXT: <PERMODULE {{.*}} op7=3 op8=[[ALIASID:[0-9]+]]/>
1111
; "another_caller" has only references but no calls.
1212
; CHECK-NEXT: <PERMODULE {{.*}} op4=3 {{.*}} op9={{[0-9]+}}/>
1313
; CHECK-NEXT: <PERMODULE {{.*}} op0=[[ALIASEEID:[0-9]+]]
@@ -20,20 +20,20 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
2020
target triple = "x86_64-unknown-linux-gnu"
2121

2222
define void @caller() {
23-
call void bitcast (void (...)* @callee to void ()*)()
24-
call void bitcast (void (...)* @analias to void ()*)()
23+
call void @callee()
24+
call void @analias()
2525
ret void
2626
}
2727

2828
define void @another_caller() {
2929
; Test calls that aren't handled either as direct or indirect.
30-
call void select (i1 icmp eq (i32* @global, i32* null), void ()* @f, void ()* @g)()
30+
call void select (i1 icmp eq (ptr @global, ptr null), ptr @f, ptr @g)()
3131
ret void
3232
}
3333

3434
declare void @callee(...)
3535

36-
@analias = alias void (...), bitcast (void ()* @aliasee to void (...)*)
36+
@analias = alias void (...), ptr @aliasee
3737

3838
define void @aliasee() {
3939
entry:

‎llvm/test/Bitcode/upgrade-invariant-group-barrier.ll

Lines changed: 11 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,19 @@
11
; RUN: opt -S < %s | FileCheck %s
22

3-
; The intrinsic firstly only took i8*, then it was made polimorphic, then
3+
; The intrinsic firstly only took ptr, then it was made polimorphic, then
44
; it was renamed to launder.invariant.group
5-
define void @test(i8* %p1, i16* %p16) {
5+
define void @test(ptr %p1, ptr %p16) {
66
; CHECK-LABEL: @test
7-
; CHECK: %p2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
8-
; CHECK: %p3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
9-
; CHECK: %p4 = call i16* @llvm.launder.invariant.group.p0i16(i16* %p16)
10-
%p2 = call i8* @llvm.invariant.group.barrier(i8* %p1)
11-
%p3 = call i8* @llvm.invariant.group.barrier.p0i8(i8* %p1)
12-
%p4 = call i16* @llvm.invariant.group.barrier.p0i16(i16* %p16)
7+
; CHECK: %p2 = call ptr @llvm.launder.invariant.group.p0(ptr %p1)
8+
; CHECK: %p3 = call ptr @llvm.launder.invariant.group.p0(ptr %p1)
9+
; CHECK: %p4 = call ptr @llvm.launder.invariant.group.p0(ptr %p16)
10+
%p2 = call ptr @llvm.invariant.group.barrier(ptr %p1)
11+
%p3 = call ptr @llvm.invariant.group.barrier.p0(ptr %p1)
12+
%p4 = call ptr @llvm.invariant.group.barrier.p0(ptr %p16)
1313
ret void
1414
}
1515

1616
; CHECK: Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
17-
; CHECK: declare i8* @llvm.launder.invariant.group.p0i8(i8*)
18-
; CHECK: Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
19-
; CHECK: declare i16* @llvm.launder.invariant.group.p0i16(i16*)
20-
declare i8* @llvm.invariant.group.barrier(i8*)
21-
declare i8* @llvm.invariant.group.barrier.p0i8(i8*)
22-
declare i16* @llvm.invariant.group.barrier.p0i16(i16*)
17+
; CHECK: declare ptr @llvm.launder.invariant.group.p0(ptr)
18+
declare ptr @llvm.invariant.group.barrier(ptr)
19+
declare ptr @llvm.invariant.group.barrier.p0(ptr)

‎llvm/test/Bitcode/upgrade-masked-keep-metadata.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,77 +1,77 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
22
; RUN: opt -S < %s | FileCheck %s
3-
define <4 x i32> @load(<4 x i32>* nocapture readonly %a0) !dbg !8 {
3+
define <4 x i32> @load(ptr nocapture readonly %a0) !dbg !8 {
44
; CHECK-LABEL: @load(
55
; CHECK-NEXT: entry:
6-
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg [[DBG19:![0-9]+]], !tbaa [[TBAA20:![0-9]+]]
6+
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg [[DBG19:![0-9]+]], !tbaa [[TBAA20:![0-9]+]]
77
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG23:![0-9]+]]
88
;
99
entry:
10-
%v0 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %a0, i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg !19, !tbaa !20
10+
%v0 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %a0, i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg !19, !tbaa !20
1111
ret <4 x i32> %v0, !dbg !23
1212
}
1313

14-
define void @store(<4 x i32> %a0, <4 x i32>* nocapture %a1) !dbg !24 {
14+
define void @store(<4 x i32> %a0, ptr nocapture %a1) !dbg !24 {
1515
; CHECK-LABEL: @store(
1616
; CHECK-NEXT: entry:
17-
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[A0:%.*]], <4 x i32>* [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg [[DBG30:![0-9]+]], !tbaa [[TBAA20]]
17+
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg [[DBG30:![0-9]+]], !tbaa [[TBAA20]]
1818
; CHECK-NEXT: ret void, !dbg [[DBG31:![0-9]+]]
1919
;
2020
entry:
21-
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a0, <4 x i32>* %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg !30, !tbaa !20
21+
call void @llvm.masked.store.v4i32.p0(<4 x i32> %a0, ptr %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg !30, !tbaa !20
2222
ret void, !dbg !31
2323
}
2424

25-
define <4 x i32> @gather(<4 x i32*> %a0) !dbg !32 {
25+
define <4 x i32> @gather(<4 x ptr> %a0) !dbg !32 {
2626
; CHECK-LABEL: @gather(
2727
; CHECK-NEXT: entry:
28-
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG35:![0-9]+]], !tbaa [[TBAA20]]
28+
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG35:![0-9]+]], !tbaa [[TBAA20]]
2929
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG36:![0-9]+]]
3030
;
3131
entry:
32-
%v0 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %a0, i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg !35, !tbaa !20
32+
%v0 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %a0, i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg !35, !tbaa !20
3333
ret <4 x i32> %v0, !dbg !36
3434
}
3535

36-
define void @scatter(<4 x i32> %a0, <4 x i32*> %a1) !dbg !37 {
36+
define void @scatter(<4 x i32> %a0, <4 x ptr> %a1) !dbg !37 {
3737
; CHECK-LABEL: @scatter(
3838
; CHECK-NEXT: entry:
39-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[A0:%.*]], <4 x i32*> [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg [[DBG41:![0-9]+]], !tbaa [[TBAA20]]
39+
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[A0:%.*]], <4 x ptr> [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg [[DBG41:![0-9]+]], !tbaa [[TBAA20]]
4040
; CHECK-NEXT: ret void, !dbg [[DBG42:![0-9]+]]
4141
;
4242
entry:
43-
call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a0, <4 x i32*> %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg !41, !tbaa !20
43+
call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a0, <4 x ptr> %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg !41, !tbaa !20
4444
ret void, !dbg !42
4545
}
4646

47-
define <4 x i32> @expandload(i32* nocapture readonly %a0) !dbg !43 {
47+
define <4 x i32> @expandload(ptr nocapture readonly %a0) !dbg !43 {
4848
; CHECK-LABEL: @expandload(
4949
; CHECK-NEXT: entry:
50-
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.expandload.v4i32(i32* [[A0:%.*]], <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG49:![0-9]+]], !tbaa [[TBAA50:![0-9]+]]
50+
; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.expandload.v4i32(ptr [[A0:%.*]], <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG49:![0-9]+]], !tbaa [[TBAA50:![0-9]+]]
5151
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG52:![0-9]+]]
5252
;
5353
entry:
54-
%v0 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* %a0, <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg !49, !tbaa !50
54+
%v0 = call <4 x i32> @llvm.masked.expandload.v4i32(ptr %a0, <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg !49, !tbaa !50
5555
ret <4 x i32> %v0, !dbg !52
5656
}
5757

58-
define void @compressstore(<4 x i32> %a0, i32* nocapture %a1) !dbg !53 {
58+
define void @compressstore(<4 x i32> %a0, ptr nocapture %a1) !dbg !53 {
5959
; CHECK-LABEL: @compressstore(
6060
; CHECK-NEXT: entry:
61-
; CHECK-NEXT: call void @llvm.masked.compressstore.v4i32(<4 x i32> [[A0:%.*]], i32* [[A1:%.*]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg [[DBG59:![0-9]+]], !tbaa [[TBAA50]]
61+
; CHECK-NEXT: call void @llvm.masked.compressstore.v4i32(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg [[DBG59:![0-9]+]], !tbaa [[TBAA50]]
6262
; CHECK-NEXT: ret void, !dbg [[DBG60:![0-9]+]]
6363
;
6464
entry:
65-
call void @llvm.masked.compressstore.v4i32(<4 x i32> %a0, i32* %a1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg !59, !tbaa !50
65+
call void @llvm.masked.compressstore.v4i32(<4 x i32> %a0, ptr %a1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg !59, !tbaa !50
6666
ret void, !dbg !60
6767
}
6868

69-
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #0
70-
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #1
71-
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32 immarg, <4 x i1>, <4 x i32>) #2
72-
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32 immarg, <4 x i1>) #3
73-
declare <4 x i32> @llvm.masked.expandload.v4i32(i32*, <4 x i1>, <4 x i32>) #2
74-
declare void @llvm.masked.compressstore.v4i32(<4 x i32>, i32*, <4 x i1>) #1
69+
declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #0
70+
declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #1
71+
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, <4 x i32>) #2
72+
declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32 immarg, <4 x i1>) #3
73+
declare <4 x i32> @llvm.masked.expandload.v4i32(ptr, <4 x i1>, <4 x i32>) #2
74+
declare void @llvm.masked.compressstore.v4i32(<4 x i32>, ptr, <4 x i1>) #1
7575

7676
attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn }
7777
attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }

‎llvm/test/Bitcode/upgrade-memory-intrinsics.ll

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -4,45 +4,45 @@
44
; to remove the alignment parameter in favour of align attributes on the pointer args.
55

66
; Make sure a non-zero alignment is propagated
7-
define void @test(i8* %p1, i8* %p2, i8* %p3) {
7+
define void @test(ptr %p1, ptr %p2, ptr %p3) {
88
; CHECK-LABEL: @test
9-
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %p1, i8 55, i64 100, i1 false)
10-
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %p1, i8* align 4 %p2, i64 50, i1 false)
11-
; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %p2, i8* align 4 %p3, i64 1000, i1 false)
12-
call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i32 4, i1 false)
13-
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i32 4, i1 false)
14-
call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i32 4, i1 false)
9+
; CHECK: call void @llvm.memset.p0.i64(ptr align 4 %p1, i8 55, i64 100, i1 false)
10+
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p1, ptr align 4 %p2, i64 50, i1 false)
11+
; CHECK: call void @llvm.memmove.p0.p0.i64(ptr align 4 %p2, ptr align 4 %p3, i64 1000, i1 false)
12+
call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i32 4, i1 false)
13+
call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i32 4, i1 false)
14+
call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i32 4, i1 false)
1515
ret void
1616
}
1717

1818
; Make sure that a zero alignment is handled properly
19-
define void @test2(i8* %p1, i8* %p2, i8* %p3) {
19+
define void @test2(ptr %p1, ptr %p2, ptr %p3) {
2020
; CHECK-LABEL: @test
21-
; CHECK: call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i1 false)
22-
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i1 false)
23-
; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i1 false)
24-
call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i32 0, i1 false)
25-
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i32 0, i1 false)
26-
call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i32 0, i1 false)
21+
; CHECK: call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i1 false)
22+
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i1 false)
23+
; CHECK: call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i1 false)
24+
call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i32 0, i1 false)
25+
call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i32 0, i1 false)
26+
call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i32 0, i1 false)
2727
ret void
2828
}
2929

3030
; Make sure that attributes are not dropped
31-
define void @test3(i8* %p1, i8* %p2, i8* %p3) {
31+
define void @test3(ptr %p1, ptr %p2, ptr %p3) {
3232
; CHECK-LABEL: @test
33-
; CHECK: call void @llvm.memset.p0i8.i64(i8* nonnull align 4 %p1, i8 signext 55, i64 zeroext 100, i1 immarg false)
34-
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %p1, i8* readonly align 4 %p2, i64 zeroext 50, i1 immarg false)
35-
; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull align 4 %p2, i8* readonly align 4 %p3, i64 zeroext 1000, i1 immarg false)
36-
call void @llvm.memset.p0i8.i64(i8* nonnull %p1, i8 signext 55, i64 zeroext 100, i32 signext 4, i1 immarg false)
37-
call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %p1, i8* readonly %p2, i64 zeroext 50, i32 signext 4, i1 immarg false)
38-
call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull %p2, i8* readonly %p3, i64 zeroext 1000, i32 signext 4, i1 immarg false)
33+
; CHECK: call void @llvm.memset.p0.i64(ptr nonnull align 4 %p1, i8 signext 55, i64 zeroext 100, i1 immarg false)
34+
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr nonnull align 4 %p1, ptr readonly align 4 %p2, i64 zeroext 50, i1 immarg false)
35+
; CHECK: call void @llvm.memmove.p0.p0.i64(ptr nonnull align 4 %p2, ptr readonly align 4 %p3, i64 zeroext 1000, i1 immarg false)
36+
call void @llvm.memset.p0.i64(ptr nonnull %p1, i8 signext 55, i64 zeroext 100, i32 signext 4, i1 immarg false)
37+
call void @llvm.memcpy.p0.p0.i64(ptr nonnull %p1, ptr readonly %p2, i64 zeroext 50, i32 signext 4, i1 immarg false)
38+
call void @llvm.memmove.p0.p0.i64(ptr nonnull %p2, ptr readonly %p3, i64 zeroext 1000, i32 signext 4, i1 immarg false)
3939
ret void
4040
}
4141

42-
; CHECK: declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
43-
; CHECK: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
44-
; CHECK: declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg)
45-
declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i32, i1)
46-
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly , i8* nocapture readonly, i64, i32, i1)
47-
declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1)
42+
; CHECK: declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
43+
; CHECK: declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
44+
; CHECK: declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg)
45+
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i32, i1)
46+
declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly , ptr nocapture readonly, i64, i32, i1)
47+
declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32, i1)
4848

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