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[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
Most places assign Opcode right after assigning every other bit in Inst. I don't think treating Opcode separately adds much value. It doesn't hide what bits belong to the opcode since every other bits is listed. This makes RVInst consistent with RVInst16 subclasss which already assign Inst{1-0} directly. Reviewed By: asb, wangpc Differential Revision: https://reviews.llvm.org/D155797
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-49
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7 files changed

+45
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‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -224,10 +224,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
224224
// to build the decode table.
225225
field bits<32> SoftFail = 0;
226226
let Size = 4;
227-
228-
bits<7> Opcode = 0;
229-
230-
let Inst{6-0} = Opcode;
231227
}
232228

233229
// Pseudo instructions
@@ -289,7 +285,7 @@ class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
289285
let Inst{19-15} = rs1;
290286
let Inst{14-12} = funct3;
291287
let Inst{11-7} = rd;
292-
let Opcode = opcode.Value;
288+
let Inst{6-0} = opcode.Value;
293289
}
294290

295291
class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
@@ -306,7 +302,7 @@ class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
306302
let Inst{19-15} = rs1;
307303
let Inst{14-12} = funct3;
308304
let Inst{11-7} = rd;
309-
let Opcode = opcode.Value;
305+
let Inst{6-0} = opcode.Value;
310306
}
311307

312308
class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
@@ -324,7 +320,7 @@ class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
324320
let Inst{19-15} = rs1;
325321
let Inst{14-12} = frm;
326322
let Inst{11-7} = rd;
327-
let Opcode = opcode.Value;
323+
let Inst{6-0} = opcode.Value;
328324
}
329325

330326
class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
@@ -342,7 +338,7 @@ class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
342338
let Inst{19-15} = rs1;
343339
let Inst{14-12} = funct3;
344340
let Inst{11-7} = rd;
345-
let Opcode = opcode.Value;
341+
let Inst{6-0} = opcode.Value;
346342
}
347343

348344
class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
@@ -358,7 +354,7 @@ class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
358354
let Inst{19-15} = rs1;
359355
let Inst{14-12} = frm;
360356
let Inst{11-7} = rd;
361-
let Opcode = opcode.Value;
357+
let Inst{6-0} = opcode.Value;
362358
}
363359

364360
class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -372,7 +368,7 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
372368
let Inst{19-15} = rs1;
373369
let Inst{14-12} = funct3;
374370
let Inst{11-7} = rd;
375-
let Opcode = opcode.Value;
371+
let Inst{6-0} = opcode.Value;
376372
}
377373

378374
class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
@@ -388,7 +384,7 @@ class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
388384
let Inst{19-15} = rs1;
389385
let Inst{14-12} = funct3;
390386
let Inst{11-7} = rd;
391-
let Opcode = opcode.Value;
387+
let Inst{6-0} = opcode.Value;
392388
}
393389

394390
class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
@@ -403,7 +399,7 @@ class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
403399
let Inst{19-15} = rs1;
404400
let Inst{14-12} = funct3;
405401
let Inst{11-7} = rd;
406-
let Opcode = opcode.Value;
402+
let Inst{6-0} = opcode.Value;
407403
}
408404

409405
class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -418,7 +414,7 @@ class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
418414
let Inst{19-15} = rs1;
419415
let Inst{14-12} = funct3;
420416
let Inst{11-7} = imm12{4-0};
421-
let Opcode = opcode.Value;
417+
let Inst{6-0} = opcode.Value;
422418
}
423419

424420
class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
@@ -435,7 +431,7 @@ class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
435431
let Inst{14-12} = funct3;
436432
let Inst{11-8} = imm12{3-0};
437433
let Inst{7} = imm12{10};
438-
let Opcode = opcode.Value;
434+
let Inst{6-0} = opcode.Value;
439435
}
440436

441437
class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -446,7 +442,7 @@ class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
446442

447443
let Inst{31-12} = imm20;
448444
let Inst{11-7} = rd;
449-
let Opcode = opcode.Value;
445+
let Inst{6-0} = opcode.Value;
450446
}
451447

452448
class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
@@ -460,7 +456,7 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
460456
let Inst{20} = imm20{10};
461457
let Inst{19-12} = imm20{18-11};
462458
let Inst{11-7} = rd;
463-
let Opcode = opcode.Value;
459+
let Inst{6-0} = opcode.Value;
464460
}
465461

466462
//===----------------------------------------------------------------------===//
@@ -482,7 +478,7 @@ class DirectiveInsnR<dag outs, dag ins, string argstr>
482478
let Inst{19-15} = rs1;
483479
let Inst{14-12} = funct3;
484480
let Inst{11-7} = rd;
485-
let Opcode = opcode;
481+
let Inst{6-0} = opcode;
486482

487483
let AsmString = ".insn r " # argstr;
488484
}
@@ -504,7 +500,7 @@ class DirectiveInsnR4<dag outs, dag ins, string argstr>
504500
let Inst{19-15} = rs1;
505501
let Inst{14-12} = funct3;
506502
let Inst{11-7} = rd;
507-
let Opcode = opcode;
503+
let Inst{6-0} = opcode;
508504

509505
let AsmString = ".insn r4 " # argstr;
510506
}
@@ -522,7 +518,7 @@ class DirectiveInsnI<dag outs, dag ins, string argstr>
522518
let Inst{19-15} = rs1;
523519
let Inst{14-12} = funct3;
524520
let Inst{11-7} = rd;
525-
let Opcode = opcode;
521+
let Inst{6-0} = opcode;
526522

527523
let AsmString = ".insn i " # argstr;
528524
}
@@ -541,7 +537,7 @@ class DirectiveInsnS<dag outs, dag ins, string argstr>
541537
let Inst{19-15} = rs1;
542538
let Inst{14-12} = funct3;
543539
let Inst{11-7} = imm12{4-0};
544-
let Opcode = opcode;
540+
let Inst{6-0} = opcode;
545541

546542
let AsmString = ".insn s " # argstr;
547543
}
@@ -562,7 +558,7 @@ class DirectiveInsnB<dag outs, dag ins, string argstr>
562558
let Inst{14-12} = funct3;
563559
let Inst{11-8} = imm12{3-0};
564560
let Inst{7} = imm12{10};
565-
let Opcode = opcode;
561+
let Inst{6-0} = opcode;
566562

567563
let AsmString = ".insn b " # argstr;
568564
}
@@ -576,7 +572,7 @@ class DirectiveInsnU<dag outs, dag ins, string argstr>
576572

577573
let Inst{31-12} = imm20;
578574
let Inst{11-7} = rd;
579-
let Opcode = opcode;
575+
let Inst{6-0} = opcode;
580576

581577
let AsmString = ".insn u " # argstr;
582578
}
@@ -590,7 +586,7 @@ class DirectiveInsnJ<dag outs, dag ins, string argstr>
590586

591587
let Inst{31-12} = imm20;
592588
let Inst{11-7} = rd;
593-
let Opcode = opcode;
589+
let Inst{6-0} = opcode;
594590

595591
let AsmString = ".insn j " # argstr;
596592
}

‎llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
6666
let Inst{19-15} = uimm;
6767
let Inst{14-12} = OPCFG.Value;
6868
let Inst{11-7} = rd;
69-
let Opcode = OPC_OP_V.Value;
69+
let Inst{6-0} = OPC_OP_V.Value;
7070

7171
let Defs = [VTYPE, VL];
7272
}
@@ -82,7 +82,7 @@ class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
8282
let Inst{19-15} = rs1;
8383
let Inst{14-12} = OPCFG.Value;
8484
let Inst{11-7} = rd;
85-
let Opcode = OPC_OP_V.Value;
85+
let Inst{6-0} = OPC_OP_V.Value;
8686

8787
let Defs = [VTYPE, VL];
8888
}
@@ -99,7 +99,7 @@ class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
9999
let Inst{19-15} = rs1;
100100
let Inst{14-12} = OPCFG.Value;
101101
let Inst{11-7} = rd;
102-
let Opcode = OPC_OP_V.Value;
102+
let Inst{6-0} = OPC_OP_V.Value;
103103

104104
let Defs = [VTYPE, VL];
105105
}
@@ -118,7 +118,7 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
118118
let Inst{19-15} = vs1;
119119
let Inst{14-12} = opv.Value;
120120
let Inst{11-7} = vd;
121-
let Opcode = OPC_OP_V.Value;
121+
let Inst{6-0} = OPC_OP_V.Value;
122122

123123
let Uses = [VTYPE, VL];
124124
let RVVConstraint = VMConstraint;
@@ -138,7 +138,7 @@ class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
138138
let Inst{19-15} = rs1;
139139
let Inst{14-12} = opv.Value;
140140
let Inst{11-7} = vd;
141-
let Opcode = OPC_OP_V.Value;
141+
let Inst{6-0} = OPC_OP_V.Value;
142142

143143
let Uses = [VTYPE, VL];
144144
let RVVConstraint = VMConstraint;
@@ -157,7 +157,7 @@ class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
157157
let Inst{19-15} = rs1;
158158
let Inst{14-12} = opv.Value;
159159
let Inst{11-7} = vd;
160-
let Opcode = OPC_OP_V.Value;
160+
let Inst{6-0} = OPC_OP_V.Value;
161161

162162
let Uses = [VTYPE, VL];
163163
let RVVConstraint = VMConstraint;
@@ -177,7 +177,7 @@ class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
177177
let Inst{19-15} = imm;
178178
let Inst{14-12} = OPIVI.Value;
179179
let Inst{11-7} = vd;
180-
let Opcode = OPC_OP_V.Value;
180+
let Inst{6-0} = OPC_OP_V.Value;
181181

182182
let Uses = [VTYPE, VL];
183183
let RVVConstraint = VMConstraint;
@@ -196,7 +196,7 @@ class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
196196
let Inst{19-15} = vs1;
197197
let Inst{14-12} = opv.Value;
198198
let Inst{11-7} = vd;
199-
let Opcode = OPC_OP_V.Value;
199+
let Inst{6-0} = OPC_OP_V.Value;
200200

201201
let Uses = [VTYPE, VL];
202202
let RVVConstraint = VMConstraint;
@@ -218,7 +218,7 @@ class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
218218
let Inst{19-15} = rs1;
219219
let Inst{14-12} = width;
220220
let Inst{11-7} = vd;
221-
let Opcode = OPC_LOAD_FP.Value;
221+
let Inst{6-0} = OPC_LOAD_FP.Value;
222222

223223
let Uses = [VTYPE, VL];
224224
let RVVConstraint = VMConstraint;
@@ -240,7 +240,7 @@ class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
240240
let Inst{19-15} = rs1;
241241
let Inst{14-12} = width;
242242
let Inst{11-7} = vd;
243-
let Opcode = OPC_LOAD_FP.Value;
243+
let Inst{6-0} = OPC_LOAD_FP.Value;
244244

245245
let Uses = [VTYPE, VL];
246246
let RVVConstraint = VMConstraint;
@@ -262,7 +262,7 @@ class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
262262
let Inst{19-15} = rs1;
263263
let Inst{14-12} = width;
264264
let Inst{11-7} = vd;
265-
let Opcode = OPC_LOAD_FP.Value;
265+
let Inst{6-0} = OPC_LOAD_FP.Value;
266266

267267
let Uses = [VTYPE, VL];
268268
let RVVConstraint = VMConstraint;
@@ -284,7 +284,7 @@ class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
284284
let Inst{19-15} = rs1;
285285
let Inst{14-12} = width;
286286
let Inst{11-7} = vs3;
287-
let Opcode = OPC_STORE_FP.Value;
287+
let Inst{6-0} = OPC_STORE_FP.Value;
288288

289289
let Uses = [VTYPE, VL];
290290
}
@@ -305,7 +305,7 @@ class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
305305
let Inst{19-15} = rs1;
306306
let Inst{14-12} = width;
307307
let Inst{11-7} = vs3;
308-
let Opcode = OPC_STORE_FP.Value;
308+
let Inst{6-0} = OPC_STORE_FP.Value;
309309

310310
let Uses = [VTYPE, VL];
311311
}
@@ -326,7 +326,7 @@ class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
326326
let Inst{19-15} = rs1;
327327
let Inst{14-12} = width;
328328
let Inst{11-7} = vs3;
329-
let Opcode = OPC_STORE_FP.Value;
329+
let Inst{6-0} = OPC_STORE_FP.Value;
330330

331331
let Uses = [VTYPE, VL];
332332
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ class CVInstMac<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
7979
let Inst{19-15} = rs1;
8080
let Inst{14-12} = funct3;
8181
let Inst{11-7} = rd;
82-
let Opcode = OPC_CUSTOM_1.Value;
82+
let Inst{6-0} = OPC_CUSTOM_1.Value;
8383
let DecoderNamespace = "XCVmac";
8484
}
8585

@@ -97,7 +97,7 @@ class CVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
9797
let Inst{19-15} = rs1;
9898
let Inst{14-12} = funct3;
9999
let Inst{11-7} = rd;
100-
let Opcode = OPC_CUSTOM_2.Value;
100+
let Inst{6-0} = OPC_CUSTOM_2.Value;
101101
let DecoderNamespace = "XCVmac";
102102
}
103103

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
8282
let Inst{19-15} = rs1;
8383
let Inst{14-12} = funct3;
8484
let Inst{11-7} = rd;
85-
let Opcode = OPC_CUSTOM_2.Value;
85+
let Inst{6-0} = OPC_CUSTOM_2.Value;
8686

8787
let Uses = [VTYPE, VL];
8888
let RVVConstraint = NoConstraint;
@@ -105,7 +105,7 @@ class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
105105
let Inst{19-15} = rs1;
106106
let Inst{14-12} = funct3;
107107
let Inst{11-7} = rd;
108-
let Opcode = OPC_CUSTOM_2.Value;
108+
let Inst{6-0} = OPC_CUSTOM_2.Value;
109109

110110
let Uses = [VTYPE, VL];
111111
let RVVConstraint = NoConstraint;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,15 +37,15 @@ class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
3737
string opcodestr, string argstr>
3838
: RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
3939
let Inst{26} = 0;
40-
let Opcode = OPC_CUSTOM_0.Value;
40+
let Inst{6-0} = OPC_CUSTOM_0.Value;
4141
let DecoderNamespace = "THeadV";
4242
}
4343

4444
class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
4545
string opcodestr, string argstr>
4646
: RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
4747
let Inst{26} = 1;
48-
let Opcode = OPC_CUSTOM_0.Value;
48+
let Inst{6-0} = OPC_CUSTOM_0.Value;
4949
let DecoderNamespace = "THeadV";
5050
}
5151

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode
6565
let Inst{19-15} = imm;
6666
let Inst{14-12} = funct3;
6767
let Inst{11-7} = rd;
68-
let Opcode = opcode.Value;
68+
let Inst{6-0} = opcode.Value;
6969
}
7070

7171
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,

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