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[RISCV][NFC] Make interleaved access test more vectorizable
The previous test case stored the result of a deinterleaved load and add into the same source address, which resulted in some scatters which we weren't testing for and made the tests harder to understand. Store it at a separate address, which will make the tests easier to read when the cost model is changed after D145085 is landed Reviewed By: reames Differential Revision: https://reviews.llvm.org/D146442
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‎llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll

Lines changed: 34 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -395,38 +395,39 @@ exit:
395395
ret void
396396
}
397397

398-
define void @combine_load_factor2_i32(ptr %p) {
398+
define void @combine_load_factor2_i32(ptr noalias %p, ptr noalias %q) {
399399
; CHECK-LABEL: @combine_load_factor2_i32(
400400
; CHECK-NEXT: entry:
401401
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
402402
; CHECK: vector.ph:
403403
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
404404
; CHECK: vector.body:
405405
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
406-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
407-
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
408-
; CHECK-NEXT: [[TMP0:%.*]] = shl <4 x i64> [[VEC_IND]], <i64 1, i64 1, i64 1, i64 1>
409-
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> [[STEP_ADD]], <i64 1, i64 1, i64 1, i64 1>
410-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[P:%.*]], <4 x i64> [[TMP0]]
411-
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[P]], <4 x i64> [[TMP1]]
412-
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x ptr> [[TMP2]], i32 0
413-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
414-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x ptr> [[TMP3]], i32 0
415-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
416-
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP5]], align 4
417-
; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <8 x i32>, ptr [[TMP7]], align 4
406+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
407+
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4
408+
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP0]], 1
409+
; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP1]], 1
410+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP2]]
411+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[P]], i64 [[TMP3]]
412+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
413+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
414+
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP6]], align 4
415+
; CHECK-NEXT: [[WIDE_VEC1:%.*]] = load <8 x i32>, ptr [[TMP7]], align 4
418416
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
419-
; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <8 x i32> [[WIDE_VEC2]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
420-
; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
421-
; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <8 x i32> [[WIDE_VEC2]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
422-
; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[STRIDED_VEC]], [[STRIDED_VEC4]]
423-
; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[STRIDED_VEC3]], [[STRIDED_VEC5]]
424-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP8]], <4 x ptr> [[TMP2]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
425-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP9]], <4 x ptr> [[TMP3]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
417+
; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <8 x i32> [[WIDE_VEC1]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
418+
; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
419+
; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x i32> [[WIDE_VEC1]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
420+
; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[STRIDED_VEC]], [[STRIDED_VEC3]]
421+
; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[STRIDED_VEC2]], [[STRIDED_VEC4]]
422+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[Q:%.*]], i64 [[TMP0]]
423+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[Q]], i64 [[TMP1]]
424+
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP10]], i32 0
425+
; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP12]], align 4
426+
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP10]], i32 4
427+
; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[TMP13]], align 4
426428
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
427-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD]], <i64 4, i64 4, i64 4, i64 4>
428-
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
429-
; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
429+
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
430+
; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
430431
; CHECK: middle.block:
431432
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, 1024
432433
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
@@ -442,7 +443,8 @@ define void @combine_load_factor2_i32(ptr %p) {
442443
; CHECK-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET1]]
443444
; CHECK-NEXT: [[X1:%.*]] = load i32, ptr [[Q1]], align 4
444445
; CHECK-NEXT: [[RES:%.*]] = add i32 [[X0]], [[X1]]
445-
; CHECK-NEXT: store i32 [[RES]], ptr [[Q0]], align 4
446+
; CHECK-NEXT: [[DST:%.*]] = getelementptr i32, ptr [[Q]], i64 [[I]]
447+
; CHECK-NEXT: store i32 [[RES]], ptr [[DST]], align 4
446448
; CHECK-NEXT: [[NEXTI]] = add i64 [[I]], 1
447449
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024
448450
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -464,7 +466,8 @@ loop:
464466

465467
%res = add i32 %x0, %x1
466468

467-
store i32 %res, ptr %q0
469+
%dst = getelementptr i32, ptr %q, i64 %i
470+
store i32 %res, ptr %dst
468471

469472
%nexti = add i64 %i, 1
470473
%done = icmp eq i64 %nexti, 1024
@@ -473,7 +476,7 @@ exit:
473476
ret void
474477
}
475478

476-
define void @combine_load_factor2_i64(ptr %p) {
479+
define void @combine_load_factor2_i64(ptr noalias %p, ptr noalias %q) {
477480
; CHECK-LABEL: @combine_load_factor2_i64(
478481
; CHECK-NEXT: entry:
479482
; CHECK-NEXT: br label [[LOOP:%.*]]
@@ -486,7 +489,8 @@ define void @combine_load_factor2_i64(ptr %p) {
486489
; CHECK-NEXT: [[Q1:%.*]] = getelementptr i64, ptr [[P]], i64 [[OFFSET1]]
487490
; CHECK-NEXT: [[X1:%.*]] = load i64, ptr [[Q1]], align 4
488491
; CHECK-NEXT: [[RES:%.*]] = add i64 [[X0]], [[X1]]
489-
; CHECK-NEXT: store i64 [[RES]], ptr [[Q0]], align 4
492+
; CHECK-NEXT: [[DST:%.*]] = getelementptr i64, ptr [[Q:%.*]], i64 [[I]]
493+
; CHECK-NEXT: store i64 [[RES]], ptr [[DST]], align 4
490494
; CHECK-NEXT: [[NEXTI]] = add i64 [[I]], 1
491495
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024
492496
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
@@ -508,11 +512,13 @@ loop:
508512

509513
%res = add i64 %x0, %x1
510514

511-
store i64 %res, ptr %q0
515+
%dst = getelementptr i64, ptr %q, i64 %i
516+
store i64 %res, ptr %dst
512517

513518
%nexti = add i64 %i, 1
514519
%done = icmp eq i64 %nexti, 1024
515520
br i1 %done, label %exit, label %loop
516521
exit:
517522
ret void
518523
}
524+

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