@@ -111,7 +111,7 @@ void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferS
111
111
// // half duplex operation, clear output enable bit
112
112
// palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE;
113
113
// }
114
- NF_SpiDriver_Receive (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize , SpiTransferCompleteCallback);
114
+ NF_SpiDriver_MReceive (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize , SpiTransferCompleteCallback);
115
115
}
116
116
else
117
117
{
@@ -325,7 +325,7 @@ HRESULT CPU_SPI_nWrite_nRead(
325
325
{
326
326
// Full duplex
327
327
// Uses the largest buffer size as transfer size
328
- NF_SpiDriver_TransferBlocking (
328
+ NF_SpiDriver_MTransferB (
329
329
palSpi->Handle ,
330
330
palSpi->WriteBuffer ,
331
331
palSpi->ReadBuffer ,
@@ -340,7 +340,7 @@ HRESULT CPU_SPI_nWrite_nRead(
340
340
// // half duplex operation, set output enable
341
341
// palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE;
342
342
// }
343
- NF_SpiDriver_TransmitBlocking (palSpi->Handle , palSpi->WriteBuffer , palSpi->WriteSize );
343
+ NF_SpiDriver_MTransmitB (palSpi->Handle , palSpi->WriteBuffer , palSpi->WriteSize );
344
344
345
345
// receive operation
346
346
// TODO
@@ -349,7 +349,7 @@ HRESULT CPU_SPI_nWrite_nRead(
349
349
// // half duplex operation, set output enable
350
350
// palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE;
351
351
// }
352
- NF_SpiDriver_ReceiveBlocking (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize );
352
+ NF_SpiDriver_MReceiveB (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize );
353
353
}
354
354
}
355
355
else
@@ -364,7 +364,7 @@ HRESULT CPU_SPI_nWrite_nRead(
364
364
// // half duplex operation, set output enable
365
365
// palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE;
366
366
// }
367
- NF_SpiDriver_ReceiveBlocking (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize );
367
+ NF_SpiDriver_MReceiveB (palSpi->Handle , palSpi->ReadBuffer , palSpi->ReadSize );
368
368
}
369
369
else
370
370
{
@@ -375,7 +375,7 @@ HRESULT CPU_SPI_nWrite_nRead(
375
375
// half duplex operation, set output enable
376
376
// palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE;
377
377
}
378
- NF_SpiDriver_TransmitBlocking (palSpi->Handle , palSpi->WriteBuffer , palSpi->WriteSize );
378
+ NF_SpiDriver_MTransmitB (palSpi->Handle , palSpi->WriteBuffer , palSpi->WriteSize );
379
379
}
380
380
}
381
381
@@ -413,7 +413,7 @@ HRESULT CPU_SPI_nWrite_nRead(
413
413
palSpi->SequentialTxRx = false ;
414
414
415
415
// Uses the largest buffer size as transfer size
416
- NF_SpiDriver_Transfer (
416
+ NF_SpiDriver_MTransfer (
417
417
palSpi->Handle ,
418
418
palSpi->WriteBuffer ,
419
419
palSpi->ReadBuffer ,
@@ -433,7 +433,7 @@ HRESULT CPU_SPI_nWrite_nRead(
433
433
}
434
434
435
435
// receive operation will be started in the callback after the above completes
436
- NF_SpiDriver_Transmit (
436
+ NF_SpiDriver_MTransmit (
437
437
palSpi->Handle ,
438
438
palSpi->WriteBuffer ,
439
439
palSpi->WriteSize ,
@@ -449,7 +449,7 @@ HRESULT CPU_SPI_nWrite_nRead(
449
449
palSpi->SequentialTxRx = false ;
450
450
451
451
// start receive
452
- NF_SpiDriver_Receive (
452
+ NF_SpiDriver_MReceive (
453
453
palSpi->Handle ,
454
454
palSpi->ReadBuffer ,
455
455
palSpi->ReadSize ,
@@ -461,7 +461,7 @@ HRESULT CPU_SPI_nWrite_nRead(
461
461
palSpi->SequentialTxRx = false ;
462
462
463
463
// start send
464
- NF_SpiDriver_Transmit (
464
+ NF_SpiDriver_MTransmit (
465
465
palSpi->Handle ,
466
466
palSpi->WriteBuffer ,
467
467
palSpi->WriteSize ,
0 commit comments