From 36f42a251d018b05c75f8444f54bb355aa06a553 Mon Sep 17 00:00:00 2001
From: Masahiro Hiramori <mhg00g13@gmail.com>
Date: Sat, 9 Nov 2024 17:30:09 +0900
Subject: [PATCH 1/2] fix syntax highlighting for implication operator

---
 syntaxes/systemverilog.tmLanguage.json | 16 ++++++++--------
 syntaxes/systemverilog.tmLanguage.yaml |  8 ++++----
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/syntaxes/systemverilog.tmLanguage.json b/syntaxes/systemverilog.tmLanguage.json
index c4c27e1b..72352642 100644
--- a/syntaxes/systemverilog.tmLanguage.json
+++ b/syntaxes/systemverilog.tmLanguage.json
@@ -878,6 +878,14 @@
     },
     "operators": {
       "patterns": [
+        {
+          "match": "\\b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\\b|:=|:/|\\|->|\\|=>|->>|\\*>|#-#|#=#|&&&",
+          "name": "keyword.operator.logical.systemverilog"
+        },
+        {
+          "match": "@|##|#|->|<->",
+          "name": "keyword.operator.channel.systemverilog"
+        },
         {
           "match": "\\+=|-=|/=|\\*=|%=|&=|\\|=|\\^=|>>>=|>>=|<<<=|<<=|<=|=",
           "name": "keyword.operator.assignment.systemverilog"
@@ -909,14 +917,6 @@
         {
           "match": "<=|<|>=|>|==\\?|!=\\?|===|!==|==|!=",
           "name": "keyword.operator.comparison.systemverilog"
-        },
-        {
-          "match": "@|##|#|->|<->",
-          "name": "keyword.operator.channel.systemverilog"
-        },
-        {
-          "match": "\\b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\\b|:=|:/|\\|->|\\|=>|->>|\\*>|#-#|#=#|&&&",
-          "name": "keyword.operator.logical.systemverilog"
         }
       ]
     },
diff --git a/syntaxes/systemverilog.tmLanguage.yaml b/syntaxes/systemverilog.tmLanguage.yaml
index 4a09b918..87ece923 100644
--- a/syntaxes/systemverilog.tmLanguage.yaml
+++ b/syntaxes/systemverilog.tmLanguage.yaml
@@ -472,6 +472,10 @@ repository:
         name: keyword.operator.quantifier.regexp
   operators:
     patterns:
+      - match: \b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\b|:=|:/|\|->|\|=>|->>|\*>|#-#|#=#|&&&
+        name: keyword.operator.logical.systemverilog
+      - match: '@|##|#|->|<->'
+        name: keyword.operator.channel.systemverilog
       - match: \+=|-=|/=|\*=|%=|&=|\|=|\^=|>>>=|>>=|<<<=|<<=|<=|=
         name: keyword.operator.assignment.systemverilog
       # - match: :|\?
@@ -490,10 +494,6 @@ repository:
         name: keyword.operator.bitwise.systemverilog
       - match: <=|<|>=|>|==\?|!=\?|===|!==|==|!=
         name: keyword.operator.comparison.systemverilog
-      - match: '@|##|#|->|<->'
-        name: keyword.operator.channel.systemverilog
-      - match: \b(?:dist|inside|with|intersect|and|or|throughout|within|first_match)\b|:=|:/|\|->|\|=>|->>|\*>|#-#|#=#|&&&
-        name: keyword.operator.logical.systemverilog
   comments:
     patterns:
       - begin: /\*

From 82c20ba8a51ae7c61b73aa446017db2af4fda2d2 Mon Sep 17 00:00:00 2001
From: Masahiro Hiramori <mhg00g13@gmail.com>
Date: Sat, 9 Nov 2024 17:30:19 +0900
Subject: [PATCH 2/2] add language example for implication operator

---
 language_examples/systemverilog/implication.sv | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 language_examples/systemverilog/implication.sv

diff --git a/language_examples/systemverilog/implication.sv b/language_examples/systemverilog/implication.sv
new file mode 100644
index 00000000..0b1f206c
--- /dev/null
+++ b/language_examples/systemverilog/implication.sv
@@ -0,0 +1,15 @@
+module test;
+
+wire a, b;
+
+property p;
+  @(posedge clk) a |-> b;
+endproperty
+a: assert property(p);
+
+property p;
+  @(posedge clk) a |=> b;
+endproperty
+a: assert property(p);
+
+endmodule