New Processors as part of thesis

[NLS-04]

Hello @mortbopet,
as part of my thesis my professor has asked me to implement further Risc-V architectures (in particular static dual-issue (VLIW)) into Ripes, most preferably as official integrations through pull requests.

As for now we have not yet determined the concrete set of processors to be implemented.
However it is most likely that they will be:

• A pipelined CPU without support for reading and writing the register file in the same clock cycle (kind of RAW hazard)
  • like the rv5s_no_fw_no_hz but with an async registerfile implementation
• VLIW pipeline (static dual-issue) architecture, where two instructions can be issued in parallel under specific conditions
  • similar to the 6 stage dual issue pipeline but with 5 stages and no way control (implicit due to the VLIW)
  • requires some additions to the gui to accommodate "parallel" assembly like shown here
    
• (uncertain?) multi-issue pipeline with out of order execution (simplified tomasulo scheme)

What do you think about this?

---

I have looked into ripes and VSRTL and have already gathered some ideas on how to integrate these additions into the standing concept.

However i also stumbled into the first problem sofar about VSRTL.
I would like to extent the current vsrtl_register.h with async registers (i.e. as non Clocked components) (as for now i think this will be the only addition to vstrl required for the processors)
However i have noticed that ripes does not integrate vsrtl from the active master branch, but an earlier timeline.
Looking into the master of vsrtl there have been some major restructuring (more project structure than code wise as it seems).

I think the more sustainable solution is to include the master branch of vstrl into ripes so that future additions can easily be implemented on the cost of having to restructure the current integration of vsrtl now.

What is your opinion on how feasible this solution is or if there are more preferable solutions.

Best regards,
Nico S.

[mortbopet]

Hi @NLS-04 - Awesome to hear that you're about to do a thesis project with Ripes! I think the processor additions sound very interesting :) You should also have a look at this PR which adds a couple of multi-cycle processors... there still needs to be some changes for that, but we can push on that since you're also about to add more stuff in the same area.

I would like to extent the current vsrtl_register.h with async registers (i.e. as non Clocked components) (as for now i think this will be the only addition to vstrl required for the processors)
However i have noticed that ripes does not integrate vsrtl from the active master branch, but an earlier timeline.

Are you sure about this? As far as i can tell, the current VSRTL tag that Ripes uses is [d497b46](https://github.com/mortbopet/VSRTL/tree/d497b46e2ecba1ca763f0573b9ce16d9e42633c5) which is also HEAD of master in the VSRTL repo.

[NLS-04]

Great to hear that this sounds interesting to you :)

As for now, we have decided to first focus on implementing the VLIW and then the OoO (Out-of-Order) CPU.

You should also have a look at this PR which adds a couple of multi-cycle processors...

Yeah we have looked into it and like how they are integrated :)
I will also take Haris & Haris and Hennessy & Patterson as inspiration for our architectures.

there still needs to be some changes for that, but we can push on that since you're also about to add more stuff in the same area.

Ah i have seen you already merged it so nvm 👍

Are you sure about this? As far as i can tell, the current VSRTL tag that Ripes uses is [d497b46](https://github.com/mortbopet/VSRTL/tree/d497b46e2ecba1ca763f0573b9ce16d9e42633c5) which is also HEAD of master in the VSRTL repo.

Oh yeah i see now 🙈, i may have mixed something up. But that's good.