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Update STM32F7 headers to v1.2.10
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-18
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‎README.md

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@@ -19,7 +19,7 @@ as the Cube release version in braces:
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- [F2: v2.2.6 created 07-April-2023](https://github.com/STMicroelectronics/STM32CubeF2)
2020
- [F3: v2.3.8 created 29-March-2024](https://github.com/STMicroelectronics/STM32CubeF3)
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- [F4: v2.6.10 created 31-May-2024](https://github.com/STMicroelectronics/STM32CubeF4)
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- [F7: v1.2.9 created 10-May-2024](https://github.com/STMicroelectronics/STM32CubeF7)
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- [F7: v1.2.10 created 25-April-2025](https://github.com/STMicroelectronics/STM32CubeF7)
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- [C0: v1.3.0 created 30-October-2024](https://github.com/STMicroelectronics/STM32CubeC0)
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- [G0: v1.4.4 created 15-December-2023](https://github.com/STMicroelectronics/STM32CubeG0)
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- [G4: v1.2.5 created 25-September-2024](https://github.com/STMicroelectronics/STM32CubeG4)

‎stm32f7xx/Include/stm32f722xx.h

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@@ -12824,7 +12824,7 @@ typedef struct
1282412824

1282512825
/******************* Bit definition for TIM_CCR5 register *******************/
1282612826
#define TIM_CCR5_CCR5_Pos (0U)
12827-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
12827+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1282812828
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1282912829
#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f723xx.h

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@@ -12846,7 +12846,7 @@ typedef struct
1284612846

1284712847
/******************* Bit definition for TIM_CCR5 register *******************/
1284812848
#define TIM_CCR5_CCR5_Pos (0U)
12849-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
12849+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f730xx.h

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@@ -13069,7 +13069,7 @@ typedef struct
1306913069

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/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
13072-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13072+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1307313073
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f732xx.h

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@@ -13047,7 +13047,7 @@ typedef struct
1304713047

1304813048
/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
13050-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13050+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f733xx.h

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@@ -13069,7 +13069,7 @@ typedef struct
1306913069

1307013070
/******************* Bit definition for TIM_CCR5 register *******************/
1307113071
#define TIM_CCR5_CCR5_Pos (0U)
13072-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13072+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1307313073
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1307413074
#define TIM_CCR5_GC5C1_Pos (29U)
1307513075
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f745xx.h

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@@ -13926,7 +13926,7 @@ typedef struct
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1392713927
/******************* Bit definition for TIM_CCR5 register *******************/
1392813928
#define TIM_CCR5_CCR5_Pos (0U)
13929-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13929+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f746xx.h

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@@ -14274,7 +14274,7 @@ typedef struct
1427414274

1427514275
/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
14277-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14277+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1427814278
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f750xx.h

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@@ -14567,7 +14567,7 @@ typedef struct
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/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
14570-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14570+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f756xx.h

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@@ -14567,7 +14567,7 @@ typedef struct
1456714567

1456814568
/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
14570-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14570+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1457114571
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1457214572
#define TIM_CCR5_GC5C1_Pos (29U)
1457314573
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f765xx.h

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@@ -14508,7 +14508,7 @@ typedef struct
1450814508

1450914509
/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
14511-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14511+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
1451414514
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f767xx.h

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@@ -14902,7 +14902,7 @@ typedef struct
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/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
14905-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14905+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f769xx.h

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@@ -14997,7 +14997,7 @@ typedef struct
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1499814998
/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
15000-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15000+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1500115001
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f777xx.h

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@@ -15195,7 +15195,7 @@ typedef struct
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/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
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#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
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#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f779xx.h

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/******************* Bit definition for TIM_CCR5 register *******************/
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#define TIM_CCR5_CCR5_Pos (0U)
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#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
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#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎stm32f7xx/Include/stm32f7xx.h

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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.2.9
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* @brief CMSIS Device version number V1.2.10
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*/
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#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
103-
#define __STM32F7_CMSIS_VERSION_SUB2 (0x09) /*!< [15:8] sub2 version */
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#define __STM32F7_CMSIS_VERSION_SUB2 (0x0A) /*!< [15:8] sub2 version */
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#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
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|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

‎stm32f7xx/Release_Notes.html

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@@ -30,7 +30,16 @@ <h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx C
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<div class="col-sm-12 col-lg-8">
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<h1 id="update-history"><strong>Update History</strong></h1>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1_2_9" checked aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
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<input type="checkbox" id="collapse-section1_2_10" checked aria-hidden="true"> <label for="collapse-section1_2_10" aria-hidden="true"><strong>V1.2.10 / 25-April-2025</strong></label>
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<div>
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<ul>
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<li>Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.</li>
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<li>Fix Capture Compare register TIMx_CCR5 defintion.</li>
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</ul>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1_2_9" aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
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<div>
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<ul>
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<li>Update GCC start-up files to call SystemInit() API <span class="citation" data-cites="Reset_Handler">@Reset_Handler</span> step: alignment with EWARM and MDK-ARM start-up files.</li>

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