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3 | 3 | * Copyright (c) 2020 Arm Limited
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4 | 4 | * Copyright (c) 2021-2023 Nordic Semiconductor ASA
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5 | 5 | * Copyright (c) 2025 Aerlync Labs Inc.
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| 6 | + * Copyright (c) 2025 Siemens Mobility GmbH |
6 | 7 | *
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7 | 8 | * Licensed under the Apache License, Version 2.0 (the "License");
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8 | 9 | * you may not use this file except in compliance with the License.
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32 | 33 | #include <zephyr/cache.h>
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33 | 34 | #endif
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34 | 35 |
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35 |
| -#if defined(CONFIG_ARM) |
| 36 | +#if defined(CONFIG_CPU_CORTEX_M) |
36 | 37 | #include <cmsis_core.h>
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37 | 38 | #endif
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38 | 39 |
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@@ -142,8 +143,19 @@ extern void *_vector_table_pointer;
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142 | 143 | #endif
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143 | 144 |
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144 | 145 | struct arm_vector_table {
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| 146 | +#ifdef CONFIG_CPU_CORTEX_M |
145 | 147 | uint32_t msp;
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146 | 148 | uint32_t reset;
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| 149 | +#else |
| 150 | + uint32_t reset; |
| 151 | + uint32_t undef_instruction; |
| 152 | + uint32_t svc; |
| 153 | + uint32_t abort_prefetch; |
| 154 | + uint32_t abort_data; |
| 155 | + uint32_t reserved; |
| 156 | + uint32_t irq; |
| 157 | + uint32_t fiq; |
| 158 | +#endif |
147 | 159 | };
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148 | 160 |
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149 | 161 | static void do_boot(struct boot_rsp *rsp)
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@@ -226,7 +238,10 @@ static void do_boot(struct boot_rsp *rsp)
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226 | 238 | #endif
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227 | 239 | #endif /* CONFIG_BOOT_INTR_VEC_RELOC */
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228 | 240 |
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| 241 | +#ifdef CONFIG_CPU_CORTEX_M |
229 | 242 | __set_MSP(vt->msp);
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| 243 | +#endif |
| 244 | + |
230 | 245 | #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
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231 | 246 | __set_CONTROL(0x00); /* application will configures core on its own */
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232 | 247 | __ISB();
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@@ -257,7 +272,17 @@ static void do_boot(struct boot_rsp *rsp)
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257 | 272 | : "r0", "r1", "r2", "r3", "memory"
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258 | 273 | );
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259 | 274 | #else
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| 275 | + |
| 276 | +#ifdef CONFIG_CPU_CORTEX_M |
260 | 277 | ((void (*)(void))vt->reset)();
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| 278 | +#else |
| 279 | + /* Some architectures like the Cortex-R run in thumb mode but reset into ARM |
| 280 | + * mode. To do the switch into ARM mode an explicit branch with exchange |
| 281 | + * instruction set is needed |
| 282 | + */ |
| 283 | + __asm__("bx %0\n" : : "r" (&vt->reset)); |
| 284 | +#endif |
| 285 | + |
261 | 286 | #endif
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262 | 287 | }
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263 | 288 |
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