SyntaxError when wishbone.Decoder data width is equal to granularity

[jfng]

Repro:

from nmigen import *
from nmigen.back import rtlil
from nmigen_soc import wishbone


class Top(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        m.submodules.dec = dec = wishbone.Decoder(addr_width=5, data_width=8, granularity=8)
        bus = wishbone.Interface(addr_width=4, data_width=8, granularity=8)
        dec.add(bus)

        return m


if __name__ == "__main__":
    print(rtlil.convert(Top()))

Output:

Traceback (most recent call last):
  File "repro.py", line 18, in <module>
    print(rtlil.convert(Top()))
  File "/home/jf/src/nmigen/nmigen/back/rtlil.py", line 1007, in convert
    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
  File "/home/jf/src/nmigen/nmigen/hdl/ir.py", line 67, in get
    obj = obj.elaborate(platform)
  File "/home/jf/src/nmigen/nmigen/hdl/dsl.py", line 484, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
  File "/home/jf/src/nmigen/nmigen/hdl/ir.py", line 67, in get
    obj = obj.elaborate(platform)
  File "/home/jf/src/nmigen-soc/nmigen_soc/wishbone/bus.py", line 247, in elaborate
    with m.Case(sub_pat[:-log2_int(self.bus.data_width // self.bus.granularity)]):
  File "/usr/lib/python3.7/contextlib.py", line 112, in __enter__
    return next(self.gen)
  File "/home/jf/src/nmigen/nmigen/hdl/dsl.py", line 283, in Case
    .format(pattern, len(switch_data["test"])))
nmigen.hdl.dsl.SyntaxError: Case pattern '' must have the same width as switch value (which is 5)