target/riscv: Add support for external triggers

lz-bro · lz-bro · commit 68ae805f973e · 2025-06-17T11:03:29.000+08:00
Add support for associating a halt group with an external trigger via a newly exposed configuration option "riscv smp_add_ext_triggers". Original merge request: riscv-collab#1179 Original author: Rob Bradford rbradford@rivosinc.com https://github.com/rbradford
diff --git a/doc/openocd.texi b/doc/openocd.texi
@@ -11616,6 +11616,19 @@ The second argument configures how OpenOCD should use the selected trigger featu
 With no parameters, prints current trigger features configuration.
 @end deffn
 
+@deffn {Command} {riscv smp_set_ext_triggers} num1 grouptype1 [num2 grouptype2] ...
+OpenOCD assigns targets of a SMP group into a RISC-V halt group. This command associates the
+supplied external trigger(s) with this halt group.
+
+When an external input trigger fires, the harts in the halt group will get halted. Similarly, all
+external output triggers will be notified when a hart in the halt group halts.
+
+The only supported value of @var{grouptype} is @option{halt_group}. RISC-V resume groups
+are not allowed because the concept of a target resuming due to a different reason than
+user's resume request is not supported by OpenOCD and GDB.
+@end deffn
+
+
 @subsection RISC-V Authentication Commands
 
 The following commands can be used to authenticate to a RISC-V system. Eg.  a
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
@@ -73,7 +73,7 @@ typedef enum {
 	RESUME_GROUP
 } grouptype_t;
 static int set_group(struct target *target, bool *supported, unsigned int group,
-		grouptype_t grouptype);
+		grouptype_t grouptype, bool is_trigger, unsigned int trigger_num);
 
 /**
  * Since almost everything can be accomplish by scanning the dbus register, all
@@ -1732,7 +1732,7 @@ static int halt_set_dcsr_ebreak(struct target *target)
 
 	if (info->haltgroup_supported) {
 		bool supported;
-		if (set_group(target, &supported, 0, HALT_GROUP) != ERROR_OK)
+		if (set_group(target, &supported, 0, HALT_GROUP, false, 0) != ERROR_OK)
 			return ERROR_FAIL;
 		if (!supported)
 			LOG_TARGET_ERROR(target, "Couldn't place hart in halt group 0. "
@@ -1754,7 +1754,7 @@ static int halt_set_dcsr_ebreak(struct target *target)
 	/* Add it back to the halt group. */
 	if (info->haltgroup_supported) {
 		bool supported;
-		if (set_group(target, &supported, target->smp, HALT_GROUP) != ERROR_OK)
+		if (set_group(target, &supported, target->smp, HALT_GROUP, false, 0) != ERROR_OK)
 			return ERROR_FAIL;
 		if (!supported)
 			LOG_TARGET_ERROR(target, "Couldn't place hart back in halt group %d. "
@@ -1785,19 +1785,27 @@ static void deinit_target(struct target *target)
 }
 
 static int set_group(struct target *target, bool *supported, unsigned int group,
-		grouptype_t grouptype)
+		grouptype_t grouptype, bool is_trigger, unsigned int trigger_num)
 {
 	uint32_t write_val = DM_DMCS2_HGWRITE;
 	assert(group <= 31);
+	assert(trigger_num < 16);
 	write_val = set_field(write_val, DM_DMCS2_GROUP, group);
 	write_val = set_field(write_val, DM_DMCS2_GROUPTYPE, (grouptype == HALT_GROUP) ? 0 : 1);
+	write_val = set_field(write_val, DM_DMCS2_DMEXTTRIGGER, trigger_num);
+	write_val = set_field(write_val, DM_DMCS2_HGSELECT,
+			    is_trigger ? DM_DMCS2_HGSELECT_TRIGGERS : DM_DMCS2_HGSELECT_HARTS);
 	if (dm_write(target, DM_DMCS2, write_val) != ERROR_OK)
 		return ERROR_FAIL;
 	uint32_t read_val;
 	if (dm_read(target, &read_val, DM_DMCS2) != ERROR_OK)
 		return ERROR_FAIL;
 	if (supported)
-		*supported = (get_field(read_val, DM_DMCS2_GROUP) == group);
+		*supported = (get_field(read_val, DM_DMCS2_GROUP) == group &&
+			get_field(read_val, DM_DMCS2_GROUPTYPE) == ((grouptype == HALT_GROUP) ? 0 : 1) &&
+			get_field(read_val, DM_DMCS2_HGSELECT) ==
+				(is_trigger ? DM_DMCS2_HGSELECT_TRIGGERS : DM_DMCS2_HGSELECT_HARTS) &&
+			get_field(read_val, DM_DMCS2_DMEXTTRIGGER) == trigger_num);
 	return ERROR_OK;
 }
 
@@ -2145,14 +2153,33 @@ static int examine(struct target *target)
 	}
 
 	if (target->smp) {
-		if (set_group(target, &info->haltgroup_supported, target->smp, HALT_GROUP) != ERROR_OK)
+		if (set_group(target, &info->haltgroup_supported, target->smp, HALT_GROUP, false, 0) != ERROR_OK)
 			return ERROR_FAIL;
 		if (info->haltgroup_supported)
 			LOG_TARGET_INFO(target, "Core %d made part of halt group %d.", info->index,
 					target->smp);
 		else
 			LOG_TARGET_INFO(target, "Core %d could not be made part of halt group %d.",
 					info->index, target->smp);
+
+		for (unsigned int i = 0; i < RISCV_MAX_EXTTRIGGERS; i++) {
+			if (r->external_triggers[i].haltgroup_num != 0 &&
+					!r->external_triggers[i].haltgroup_was_set &&
+					info->haltgroup_supported) {
+				bool supported;
+				if (set_group(target, &supported, target->smp, HALT_GROUP, true, i) != ERROR_OK)
+					return ERROR_FAIL;
+				if (supported) {
+					r->external_triggers[i].haltgroup_was_set = true;
+					LOG_TARGET_INFO(target, "External trigger %d made part of halt group %d.",
+							i, target->smp);
+				} else {
+					LOG_TARGET_WARNING(target, "External trigger %d could not be made part of halt group %d.",
+							i, target->smp);
+				}
+			}
+		}
+
 	}
 
 	/* Some regression suites rely on seeing 'Examined RISC-V core' to know
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
@@ -5588,6 +5588,51 @@ COMMAND_HANDLER(handle_riscv_virt2phys_mode)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(riscv_smp_set_ext_triggers)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	RISCV_INFO(r);
+
+	if (!target->smp) {
+		LOG_TARGET_ERROR(target, "This target does not belong to any SMP group. "
+				"Command 'riscv smp_set_ext_triggers' cannot be used.");
+		return ERROR_FAIL;
+	}
+
+	if (CMD_ARGC % 2) {
+		LOG_ERROR("Command takes an even number of parameters.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	if (CMD_ARGC > 2 * RISCV_MAX_EXTTRIGGERS) {
+		LOG_ERROR("The number of parameters must not exceed %d.", 2 * RISCV_MAX_EXTTRIGGERS);
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	unsigned int trigger_num = 0;
+	for (unsigned int i = 0; i < CMD_ARGC - 1; i += 2) {
+		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[i], trigger_num);
+		if (trigger_num > 15) {
+			LOG_ERROR("%s is not a valid external trigger number - expecting a number in range 0..15.",
+				CMD_ARGV[i + 1]);
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
+		if (!strcmp("halt_group", CMD_ARGV[i + 1])) {
+			r->external_triggers[trigger_num].haltgroup_num = target->smp;
+		} else {
+			/* Ext. triggers for resume groups are not supported: neither OpenOCD nor GDB
+			 * have a concept of hart resuming on its own due to an external reason, without
+			 * an explicit resume request. */
+			LOG_ERROR("%s is not a valid argument. "
+				"The only supported group type is 'halt_group'.", CMD_ARGV[0]);
+			return ERROR_COMMAND_ARGUMENT_INVALID;
+		}
+	}
+
+	return ERROR_OK;
+}
+
+
 static const struct command_registration riscv_exec_command_handlers[] = {
 	{
 		.name = "dump_sample_buf",
@@ -5850,6 +5895,13 @@ static const struct command_registration riscv_exec_command_handlers[] = {
 			"When off, users need to take care of memory coherency themselves, for example by using "
 			"`riscv exec_progbuf` to execute fence or CMO instructions."
 	},
+	{
+		.name = "smp_set_ext_triggers",
+		.handler = riscv_smp_set_ext_triggers,
+		.mode = COMMAND_CONFIG,
+		.usage = "num1 grouptype1 [num2 grouptype2]......",
+		.help = "Set the given external triggers to the halt group."
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
@@ -21,6 +21,7 @@ struct riscv_program;
 #define RISCV_MAX_TRIGGERS 32
 #define RISCV_MAX_HWBPS 16
 #define RISCV_MAX_DMS 100
+#define RISCV_MAX_EXTTRIGGERS 16
 
 #define DEFAULT_COMMAND_TIMEOUT_SEC 5
 
@@ -144,6 +145,17 @@ typedef struct riscv_mem_access_args {
 	uint32_t increment;
 } riscv_mem_access_args_t;
 
+struct riscv_ext_trigger {
+	bool haltgroup_was_set;
+	unsigned int haltgroup_num;
+	/*
+	In future, this can be added:
+
+	bool resumegroup_was_set;
+	unsigned int resumegroup_num;
+	 */
+};
+
 static inline bool
 riscv_mem_access_is_valid(const riscv_mem_access_args_t args)
 {
@@ -365,6 +377,8 @@ struct riscv_info {
 	bool wp_allow_ge_lt_trigger;
 
 	bool autofence;
+
+	struct riscv_ext_trigger external_triggers[RISCV_MAX_EXTTRIGGERS];
 };
 
 enum riscv_priv_mode {
