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[pre_syn] Align Yosys synthesis setups with latest prim changes
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
1 parent 1bd59e9 commit a113255

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6 files changed

+102
-107
lines changed

6 files changed

+102
-107
lines changed

‎hw/ip/aes/pre_syn/syn_yosys.sh

Lines changed: 9 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -70,13 +70,15 @@ OT_DEP_SOURCES=(
7070
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_cdc_rand_delay.sv
7171
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_reg_we_check.sv
7272
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
73-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
74-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
75-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
76-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
77-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
78-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
79-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
73+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_buf.sv
74+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_flop.sv
75+
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_flop_2sync.sv
76+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop.sv
77+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop_en.sv
78+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_and2.sv
79+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_buf.sv
80+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xor2.sv
81+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xnor2.sv
8082
)
8183

8284
# Get OpenTitan dependency packages.
@@ -107,16 +109,6 @@ for file in "${OT_DEP_SOURCES[@]}"; do
107109
$file \
108110
> $LR_SYNTH_OUT_DIR/generated/${module}.v
109111

110-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
111-
# where available.
112-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
113-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
114-
$LR_SYNTH_OUT_DIR/generated/${module}.v
115-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
116-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
117-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
118-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
119-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
120112
done
121113

122114
# Rename the prim_sparse_fsm_flop module. For some reason, sv2v decides to append a suffix.
@@ -140,17 +132,6 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
140132
$file \
141133
> $LR_SYNTH_OUT_DIR/generated/${module}.v
142134

143-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
144-
# where available.
145-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
146-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
147-
$LR_SYNTH_OUT_DIR/generated/${module}.v
148-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
149-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
150-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
151-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
152-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
153-
154135
# Rename prim_sparse_fsm_flop instances. For some reason, sv2v decides to append a suffix.
155136
sed -i 's/prim_sparse_fsm_flop_.*/prim_sparse_fsm_flop \#(/g' \
156137
$LR_SYNTH_OUT_DIR/generated/${module}.v

‎hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl

Lines changed: 24 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,14 @@ yosys "attrmap -tocase keep -imap dont_touch=\"yes\" keep=1 -imap dont_touch=\"n
3333
# Place keep_hierarchy constraints on relevant modules to prevent aggressive synthesis optimizations
3434
# across the boundaries of these modules.
3535
yosys "hierarchy -check -top $lr_synth_top_module"
36-
yosys "setattr -mod -set keep_hierarchy 1 *prim_xilinx*"
36+
yosys "setattr -mod -set keep_hierarchy 1 *prim_and2*"
37+
yosys "setattr -mod -set keep_hierarchy 1 *prim_buf*"
38+
yosys "setattr -mod -set keep_hierarchy 1 *prim_clock*"
39+
yosys "setattr -mod -set keep_hierarchy 1 *prim_flop*"
40+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xnor2*"
41+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xor2*"
3742
yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_p*"
3843
yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_n*"
39-
yosys "setattr -mod -set keep_hierarchy 1 *aes_sel_buf_chk*"
4044

4145
# Synthesize.
4246
yosys "synth -nofsm $flatten_opt -top $lr_synth_top_module"
@@ -46,18 +50,26 @@ yosys "write_verilog $lr_synth_pre_map_out"
4650

4751
# Remove keep_hierarchy constraints before writing out the netlist for Alma as it doesn't like
4852
# these constraints.
49-
yosys "setattr -mod -set keep_hierarchy 0 *prim_xilinx*"
53+
yosys "setattr -mod -set keep_hierarchy 0 *prim_and2*"
54+
yosys "setattr -mod -set keep_hierarchy 0 *prim_buf*"
55+
yosys "setattr -mod -set keep_hierarchy 0 *prim_clock*"
56+
yosys "setattr -mod -set keep_hierarchy 0 *prim_flop*"
57+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xnor2*"
58+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xor2*"
5059
yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_p*"
5160
yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_n*"
52-
yosys "setattr -mod -set keep_hierarchy 0 *aes_sel_buf_chk*"
5361

5462
yosys "write_verilog $lr_synth_alma_out"
5563

5664
# Re-add keep_hierarchy constraints for further synthesis steps.
57-
yosys "setattr -mod -set keep_hierarchy 1 *prim_xilinx*"
65+
yosys "setattr -mod -set keep_hierarchy 1 *prim_and2*"
66+
yosys "setattr -mod -set keep_hierarchy 1 *prim_buf*"
67+
yosys "setattr -mod -set keep_hierarchy 1 *prim_clock*"
68+
yosys "setattr -mod -set keep_hierarchy 1 *prim_flop*"
69+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xnor2*"
70+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xor2*"
5871
yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_p*"
5972
yosys "setattr -mod -set keep_hierarchy 1 *aes_*_fsm_n*"
60-
yosys "setattr -mod -set keep_hierarchy 1 *aes_sel_buf_chk*"
6173

6274
yosys "dfflibmap -liberty $lr_synth_cell_library_path"
6375
yosys "opt"
@@ -71,10 +83,14 @@ if { $lr_synth_timing_run } {
7183
}
7284

7385
# Remove keep_hierarchy constraints before the final flattening step. We're done optimizing.
74-
yosys "setattr -mod -set keep_hierarchy 0 *prim_xilinx*"
86+
yosys "setattr -mod -set keep_hierarchy 0 *prim_and2*"
87+
yosys "setattr -mod -set keep_hierarchy 0 *prim_buf*"
88+
yosys "setattr -mod -set keep_hierarchy 0 *prim_clock*"
89+
yosys "setattr -mod -set keep_hierarchy 0 *prim_flop*"
90+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xnor2*"
91+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xor2*"
7592
yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_p*"
7693
yosys "setattr -mod -set keep_hierarchy 0 *aes_*_fsm_n*"
77-
yosys "setattr -mod -set keep_hierarchy 0 *aes_sel_buf_chk*"
7894

7995
# Final flattening.
8096
if { $lr_synth_flatten } {

‎hw/ip/kmac/pre_syn/syn_yosys.sh

Lines changed: 10 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -72,13 +72,15 @@ OT_DEP_SOURCES=(
7272
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
7373
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_mubi4_sender.sv
7474
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync_cnt.sv
75-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
76-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
77-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
78-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
79-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
80-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
81-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
75+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_buf.sv
76+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_flop.sv
77+
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_flop_2sync.sv
78+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop.sv
79+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop_en.sv
80+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_and2.sv
81+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_buf.sv
82+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xor2.sv
83+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xnor2.sv
8284
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_adapter_sram.sv
8385
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_sram_byte.sv
8486
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_socket_1n.sv
@@ -124,16 +126,6 @@ for file in "${OT_DEP_SOURCES[@]}"; do
124126
$file \
125127
> $LR_SYNTH_OUT_DIR/generated/${module}.v
126128

127-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
128-
# where available.
129-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
130-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
131-
$LR_SYNTH_OUT_DIR/generated/${module}.v
132-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
133-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
134-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
135-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
136-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
137129
done
138130

139131
# Rename the prim_sparse_fsm_flop module. For some reason, sv2v decides to append a suffix.
@@ -157,17 +149,6 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
157149
$file \
158150
> $LR_SYNTH_OUT_DIR/generated/${module}.v
159151

160-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
161-
# where available.
162-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
163-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
164-
$LR_SYNTH_OUT_DIR/generated/${module}.v
165-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
166-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
167-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
168-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
169-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
170-
171152
# Rename prim_sparse_fsm_flop instances. For some reason, sv2v decides to append a suffix.
172153
sed -i 's/prim_sparse_fsm_flop_.*/prim_sparse_fsm_flop \#(/g' \
173154
$LR_SYNTH_OUT_DIR/generated/${module}.v
@@ -178,6 +159,7 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
178159
sed -i '/\.StateEnumT_StateWidth(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v
179160
sed -i '/\.StateEnumT_StateWidthPad(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v
180161
sed -i '/\.StateEnumT_sha3_pkg.*(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v
162+
sed -i '/\.StateEnumT_kmac_pkg.*(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v
181163
done
182164

183165
#-------------------------------------------------------------------------

‎hw/ip/kmac/pre_syn/tcl/yosys_run_synth.tcl

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,12 @@ yosys "attrmap -tocase keep -imap dont_touch=\"yes\" keep=1 -imap dont_touch=\"n
3131
# Place keep_hierarchy constraints on relevant modules to prevent aggressive synthesis optimizations
3232
# across the boundaries of these modules.
3333
yosys "hierarchy -check -top $lr_synth_top_module"
34-
yosys "setattr -mod -set keep_hierarchy 1 *prim_xilinx*"
34+
yosys "setattr -mod -set keep_hierarchy 1 *prim_and2*"
35+
yosys "setattr -mod -set keep_hierarchy 1 *prim_buf*"
36+
yosys "setattr -mod -set keep_hierarchy 1 *prim_clock*"
37+
yosys "setattr -mod -set keep_hierarchy 1 *prim_flop*"
38+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xnor2*"
39+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xor2*"
3540

3641
# Synthesize.
3742
yosys "synth -nofsm $flatten_opt -top $lr_synth_top_module"
@@ -41,12 +46,22 @@ yosys "write_verilog $lr_synth_pre_map_out"
4146

4247
# Remove keep_hierarchy constraints before writing out the netlist for Alma as it doesn't like
4348
# these constraints.
44-
yosys "setattr -mod -set keep_hierarchy 0 *prim_xilinx*"
49+
yosys "setattr -mod -set keep_hierarchy 0 *prim_and2*"
50+
yosys "setattr -mod -set keep_hierarchy 0 *prim_buf*"
51+
yosys "setattr -mod -set keep_hierarchy 0 *prim_clock*"
52+
yosys "setattr -mod -set keep_hierarchy 0 *prim_flop*"
53+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xnor2*"
54+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xor2*"
4555

4656
yosys "write_verilog $lr_synth_alma_out"
4757

4858
# Re-add keep_hierarchy constraints for further synthesis steps.
49-
yosys "setattr -mod -set keep_hierarchy 1 *prim_xilinx*"
59+
yosys "setattr -mod -set keep_hierarchy 1 *prim_and2*"
60+
yosys "setattr -mod -set keep_hierarchy 1 *prim_buf*"
61+
yosys "setattr -mod -set keep_hierarchy 1 *prim_clock*"
62+
yosys "setattr -mod -set keep_hierarchy 1 *prim_flop*"
63+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xnor2*"
64+
yosys "setattr -mod -set keep_hierarchy 1 *prim_xor2*"
5065

5166
yosys "dfflibmap -liberty $lr_synth_cell_library_path"
5267
yosys "opt"
@@ -60,7 +75,12 @@ if { $lr_synth_timing_run } {
6075
}
6176

6277
# Remove keep_hierarchy constraints before the final flattening step. We're done optimizing.
63-
yosys "setattr -mod -set keep_hierarchy 0 *prim_xilinx*"
78+
yosys "setattr -mod -set keep_hierarchy 0 *prim_and2*"
79+
yosys "setattr -mod -set keep_hierarchy 0 *prim_buf*"
80+
yosys "setattr -mod -set keep_hierarchy 0 *prim_clock*"
81+
yosys "setattr -mod -set keep_hierarchy 0 *prim_flop*"
82+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xnor2*"
83+
yosys "setattr -mod -set keep_hierarchy 0 *prim_xor2*"
6484

6585
# Final flattening.
6686
if { $lr_synth_flatten } {

‎hw/ip/otbn/pre_syn/syn_yosys.sh

Lines changed: 11 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -71,14 +71,15 @@ OT_DEP_SOURCES=(
7171
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_onehot_check.sv
7272
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_mubi4_sender.sv
7373
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_fifo_sync_cnt.sv
74-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop.sv
75-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_flop_2sync.sv
76-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop.sv
77-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_flop_en.sv
78-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_buf.sv
79-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xor2.sv
80-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_xnor2.sv
81-
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xilinx_and2.sv
74+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_buf.sv
75+
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_sec_anchor_flop.sv
76+
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_flop_2sync.sv
77+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop.sv
78+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_flop_en.sv
79+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_and2.sv
80+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_buf.sv
81+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xor2.sv
82+
"$LR_SYNTH_SRC_DIR"/../prim_xilinx/rtl/prim_xnor2.sv
8283
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_adapter_sram.sv
8384
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_sram_byte.sv
8485
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/tlul_socket_1n.sv
@@ -98,7 +99,7 @@ OT_DEP_SOURCES=(
9899
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_xoshiro256pp.sv
99100
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_ram_1p_scr.sv
100101
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_ram_1p_adv.sv
101-
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_generic_ram_1p.sv
102+
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/prim_ram_1p.sv
102103
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_subst_perm.sv
103104
"$LR_SYNTH_SRC_DIR"/../prim/rtl/prim_prince.sv
104105
)
@@ -112,6 +113,7 @@ OT_DEP_PACKAGES=(
112113
"$LR_SYNTH_SRC_DIR"/../lc_ctrl/rtl/*_pkg.sv
113114
"$LR_SYNTH_SRC_DIR"/../tlul/rtl/*_pkg.sv
114115
"$LR_SYNTH_SRC_DIR"/../prim/rtl/*_pkg.sv
116+
"$LR_SYNTH_SRC_DIR"/../prim_generic/rtl/*_pkg.sv
115117
"$LR_SYNTH_SRC_DIR"/../keymgr/rtl/*_pkg.sv
116118
"$LR_SYNTH_SRC_DIR"/../otp_ctrl/rtl/*_pkg.sv
117119
)
@@ -132,19 +134,6 @@ for file in "${OT_DEP_SOURCES[@]}"; do
132134
$file \
133135
> $LR_SYNTH_OUT_DIR/generated/${module}.v
134136

135-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
136-
# where available.
137-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
138-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
139-
$LR_SYNTH_OUT_DIR/generated/${module}.v
140-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
141-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
142-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
143-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
144-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
145-
sed -i 's/prim_and2/prim_xilinx_and2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
146-
sed -i 's/prim_ram_1p/prim_generic_ram_1p/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
147-
148137
# Remove calls to $value$plusargs(). Yosys doesn't seem to support this.
149138
sed -i '/$value$plusargs(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v
150139
done
@@ -170,19 +159,6 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do
170159
$file \
171160
> $LR_SYNTH_OUT_DIR/generated/${module}.v
172161

173-
# Make sure auto-generated primitives are resolved to generic or Xilinx-specific primitives
174-
# where available.
175-
sed -i 's/prim_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
176-
sed -i 's/prim_xilinx_flop_2sync/prim_generic_flop_2sync/g' \
177-
$LR_SYNTH_OUT_DIR/generated/${module}.v
178-
sed -i 's/prim_sec_anchor_flop/prim_xilinx_flop/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
179-
sed -i 's/prim_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
180-
sed -i 's/prim_sec_anchor_buf/prim_xilinx_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
181-
sed -i 's/prim_xor2/prim_xilinx_xor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
182-
sed -i 's/prim_xnor2/prim_xilinx_xnor2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
183-
sed -i 's/prim_and2/prim_xilinx_and2/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
184-
sed -i 's/prim_ram_1p/prim_generic_ram_1p/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
185-
186162
# Rename prim_sparse_fsm_flop instances. For some reason, sv2v decides to append a suffix.
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sed -i 's/prim_sparse_fsm_flop_.*/prim_sparse_fsm_flop \#(/g' \
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$LR_SYNTH_OUT_DIR/generated/${module}.v

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