From 16ee057a5af198865345f9d456fba18da2ed4f3b Mon Sep 17 00:00:00 2001
From: Min Hsu <min.hsu@sifive.com>
Date: Tue, 8 Jul 2025 17:33:16 -0700
Subject: [PATCH] [RISCV] Add scheduling info for XSfvqmaccdod/qoq and
 XSfvfwmaccqqq instructions

---
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td    | 23 ++++-
 llvm/lib/Target/RISCV/RISCVSchedAndes45.td    |  3 +
 llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td |  3 +
 llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td  |  3 +
 llvm/lib/Target/RISCV/RISCVSchedRocket.td     |  3 +
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td    | 35 +++++++
 llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td |  3 +
 llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td |  3 +
 llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td |  3 +
 llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td |  3 +
 .../lib/Target/RISCV/RISCVSchedSpacemitX60.td |  3 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR1.td   |  3 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR345.td |  3 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR7.td   |  3 +
 .../lib/Target/RISCV/RISCVSchedTTAscalonD8.td |  3 +
 .../Target/RISCV/RISCVSchedXiangShanNanHu.td  |  3 +
 llvm/lib/Target/RISCV/RISCVScheduleXSf.td     | 30 ++++++
 .../tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s | 75 ++++++++++++++
 .../tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s  | 94 ++++++++++++++++++
 .../llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s    | 78 +++++++++++++++
 .../llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s     | 97 +++++++++++++++++++
 21 files changed, 472 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 6fe747800b5ad..e1981a6ca8901 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -167,10 +167,25 @@ multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
                                              InTyRs1, 1>;
 }
 
+// For XSfvqmaccdod/qoq and XSfvfwmaccqqq
+class SiFiveVMACCScheds<string name> {
+  defvar n = !tolower(name);
+  defvar prefix = !if(!ne(!find(n, "fw"), -1), "FW", "Q");
+  defvar suffix = !if(!ne(!find(n, "2x8x2"), -1), "DOD",
+                      !if(!eq(prefix, "Q"), "QOQ", "QQQ"));
+
+  string read = "ReadSF_V" # prefix # "MACC_" # suffix;
+  string write = "WriteSF_V" # prefix # "MACC_" # suffix;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),
-                      opcodestr, "$rd, $rs1, $rs2"> {
+                      opcodestr, "$rd, $rs1, $rs2">,
+      SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,
+                     SiFiveVMACCScheds<NAME>.read,
+                     SiFiveVMACCScheds<NAME>.read,
+                     SiFiveVMACCScheds<NAME>.read> {
   let vm = 1;
   let funct6_lo2 = funct6{1-0};
 }
@@ -373,9 +388,13 @@ multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
 }
 
 multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type> {
+  defvar SchedWriteName = SiFiveVMACCScheds<NAME>.write;
+  defvar SchedReadName = SiFiveVMACCScheds<NAME>.read;
   def "Pseudo" # NAME # "_" # mx
       : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type,
-                                       "@earlyclobber $rd">;
+                                       "@earlyclobber $rd">,
+        SchedTernary<SchedWriteName, SchedReadName, SchedReadName,
+                     SchedReadName, mx>;
 }
 
 multiclass VPseudoSiFiveVQMACCDOD {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index f42b48a1d8b83..6b2df4fe39d85 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -331,6 +331,9 @@ defm : UnsupportedSchedQ;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
index 6dd973bc1e83f..3ade5dfc0eac5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
@@ -498,4 +498,7 @@ defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 8ba4cd0acdd6c..df689b8579bef 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -274,5 +274,8 @@ defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 4c4654ba2fc0f..1d25d01ab646e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -263,5 +263,8 @@ defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 6600a00d4e098..780375b6d4fed 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1049,6 +1049,36 @@ multiclass SiFive7WriteResBase<int VLEN,
       }
     }
   }
+
+  // XSfvqmaccdod
+  foreach mx = ["M1", "M2", "M4", "M8"] in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VQMACC_DOD", [VCQ, VA1], mx,
+                          IsWorstCase=!eq(mx, "M8")>;
+  }
+
+  // XSfvqmaccqoq
+  foreach mx = ["MF2", "M1", "M2", "M4"] in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VQMACC_QOQ", [VCQ, VA1], mx,
+                          IsWorstCase=!eq(mx, "M4")>;
+  }
+
+  // XSfvfwmaccqqq
+  foreach mx = SchedMxListFW in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VFWMACC_QQQ", [VCQ, VA1], mx, IsWorstCase>;
+  }
 }
 
 //===----------------------------------------------------------------------===//
@@ -1326,6 +1356,11 @@ multiclass SiFive7ReadAdvance {
   def : ReadAdvance<ReadVMov4V, 0>;
   def : ReadAdvance<ReadVMov8V, 0>;
 
+  // SiFive VMACC
+  defm : LMULReadAdvance<"ReadSF_VQMACC_DOD",  0>;
+  defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ",  0>;
+  defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
+
   // Others
   def : ReadAdvance<ReadVMask, 0>;
   def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 370ea64699383..64e85ecb83776 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -1239,4 +1239,7 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
index 5933d73174f79..7e08c086f53d0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -359,4 +359,7 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 7c04d1c54473d..3564cfa2997d0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -1495,4 +1495,7 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index f2b660583f27f..43847a2743d83 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -1184,4 +1184,7 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 9059d5a4e497b..129c48159a5c4 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -346,6 +346,9 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
index 4aa74b020825c..7b9c852ce7a14 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -117,5 +117,8 @@ defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
index 815c2da992a11..7ae2c0dde9ef3 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
@@ -183,6 +183,9 @@ multiclass SCR_Unsupported :
   UnsupportedSchedSFB,
   UnsupportedSchedV,
   UnsupportedSchedXsfvcp,
+  UnsupportedSchedXSfvfwmaccqqq,
+  UnsupportedSchedXSfvqmaccdod,
+  UnsupportedSchedXSfvqmaccqoq,
   UnsupportedSchedZabha,
   UnsupportedSchedZba,
   UnsupportedSchedZbb,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
index decd578360753..49296c1ff75ff 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
@@ -245,6 +245,9 @@ multiclass SCR7_Unsupported {
   defm : UnsupportedSchedSFB;
   defm : UnsupportedSchedV;
   defm : UnsupportedSchedXsfvcp;
+  defm : UnsupportedSchedXSfvfwmaccqqq;
+  defm : UnsupportedSchedXSfvqmaccdod;
+  defm : UnsupportedSchedXSfvqmaccqoq;
   defm : UnsupportedSchedZabha;
   defm : UnsupportedSchedZfa;
   defm : UnsupportedSchedZfhmin;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 5322de100d0ad..98e44fd613d89 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -321,6 +321,9 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 defm : UnsupportedSchedQ;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
index 3076a2ebb813d..5b0bdd7b26aea 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -313,5 +313,8 @@ defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleXSf.td b/llvm/lib/Target/RISCV/RISCVScheduleXSf.td
index 58d508460f019..c57e25c16b84a 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleXSf.td
@@ -57,3 +57,33 @@ foreach f = ["FPR16", "FPR32", "FPR64"] in {
 }
 }
 }
+
+defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_DOD", ["M1", "M2", "M4", "M8"]>;
+defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_DOD",   ["M1", "M2", "M4", "M8"]>;
+
+multiclass UnsupportedSchedXSfvqmaccdod {
+let Unsupported = true in {
+defm : LMULWriteRes<"WriteSF_VQMACC_DOD", []>;
+defm : LMULReadAdvance<"ReadSF_VQMACC_DOD", 0>;
+} // Unsupported = true
+}
+
+defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_QOQ", ["MF2", "M1", "M2", "M4"]>;
+defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_QOQ",   ["MF2", "M1", "M2", "M4"]>;
+
+multiclass UnsupportedSchedXSfvqmaccqoq {
+let Unsupported = true in {
+defm : LMULWriteRes<"WriteSF_VQMACC_QOQ", []>;
+defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ", 0>;
+} // Unsupported = true
+}
+
+defm "" : LMULSchedWritesImpl<"WriteSF_VFWMACC_QQQ", SchedMxListFW>;
+defm "" : LMULSchedReadsImpl<"ReadSF_VFWMACC_QQQ",   SchedMxListFW>;
+
+multiclass UnsupportedSchedXSfvfwmaccqqq {
+let Unsupported = true in {
+defm : LMULWriteRes<"WriteSF_VFWMACC_QQQ", []>;
+defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
+} // Unsupported = true
+}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
new file mode 100644
index 0000000000000..76666c82af208
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfwmaccqqq' -instruction-tables=full -iterations=1 %s | \
+# RUN:   FileCheck %s
+
+vsetvli zero, zero, e16, mf4, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, mf2, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m1, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m2, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m4, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN512SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN512SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN512SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN512SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN512SiFive7VA:1
+# CHECK-NEXT: [6]   - VLEN512SiFive7VCQ:1
+# CHECK-NEXT: [7]   - VLEN512SiFive7VL:1
+# CHECK-NEXT: [8]   - VLEN512SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ    SF_VFWMACC_4x4x4           sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ    SF_VFWMACC_4x4x4           sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e16, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ    SF_VFWMACC_4x4x4           sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e16, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ    SF_VFWMACC_4x4x4           sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e16, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ    SF_VFWMACC_4x4x4           sf.vfwmacc.4x4x4	v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN512SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN512SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN512SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN512SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN512SiFive7VA
+# CHECK-NEXT: [5]   - VLEN512SiFive7VCQ
+# CHECK-NEXT: [6]   - VLEN512SiFive7VL
+# CHECK-NEXT: [7]   - VLEN512SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     5.00    -     21.00  5.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00   1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00   1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e16, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00   1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e16, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00   1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e16, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00   1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
new file mode 100644
index 0000000000000..a30ee119899a3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvqmaccqoq,+xsfvqmaccdod' -instruction-tables=full -iterations=1 %s | \
+# RUN:   FileCheck %s
+
+vsetvli zero, zero, e8, m1, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m2, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m4, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m8, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+
+vsetvli zero, zero, e8, mf2, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m1, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m2, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m4, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN512SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN512SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN512SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN512SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN512SiFive7VA:1
+# CHECK-NEXT: [6]   - VLEN512SiFive7VCQ:1
+# CHECK-NEXT: [7]   - VLEN512SiFive7VL:1
+# CHECK-NEXT: [8]   - VLEN512SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ    SF_VQMACC_2x8x2            sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ    SF_VQMACC_2x8x2            sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ    SF_VQMACC_2x8x2            sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m8, ta, ma
+# CHECK-NEXT:  1      8     16.00                        8     VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ   SF_VQMACC_2x8x2            sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ    SF_VQMACC_4x8x4            sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ    SF_VQMACC_4x8x4            sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ    SF_VQMACC_4x8x4            sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB   VSETVLI                    vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ    SF_VQMACC_4x8x4            sf.vqmacc.4x8x4	v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN512SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN512SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN512SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN512SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN512SiFive7VA
+# CHECK-NEXT: [5]   - VLEN512SiFive7VCQ
+# CHECK-NEXT: [6]   - VLEN512SiFive7VL
+# CHECK-NEXT: [7]   - VLEN512SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     8.00    -     53.00  8.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00   1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00   1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00   1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m8, ta, ma
+# CHECK-NEXT:  -      -      -      -     17.00  1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00   1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00   1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00   1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00   1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
new file mode 100644
index 0000000000000..4d1d968518890
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
@@ -0,0 +1,78 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -mattr='+xsfvfwmaccqqq' -instruction-tables=full -iterations=1 %s | \
+# RUN:   FileCheck %s
+
+vsetvli zero, zero, e16, mf4, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, mf2, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m1, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m2, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+vsetvli zero, zero, e16, m4, ta, ma
+sf.vfwmacc.4x4x4 v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4	v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     5.00    -     21.00   -     5.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     sf.vfwmacc.4x4x4	v16, v0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s
new file mode 100644
index 0000000000000..262af54508a1d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -mattr='+xsfvqmaccqoq,+xsfvqmaccdod' -instruction-tables=full -iterations=1 %s | \
+# RUN:   FileCheck %s
+
+vsetvli zero, zero, e8, m1, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m2, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m4, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+vsetvli zero, zero, e8, m8, ta, ma
+sf.vqmacc.2x8x2 v16, v0, v8
+
+vsetvli zero, zero, e8, mf2, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m1, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m2, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+vsetvli zero, zero, e8, m4, ta, ma
+sf.vqmacc.4x8x4 v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, ta, ma
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4	v16, v0, v8
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     8.00    -     53.00   -     8.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, ta, ma
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     sf.vqmacc.2x8x2	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, ta, ma
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, ta, ma
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, ta, ma
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     sf.vqmacc.4x8x4	v16, v0, v8